Gregarius » Intel Software Network Blogs

Intel Software Network Blogs (100 unread)

Skip to page: 1 2

nulstein v2 plog - fully parallel game loop demo

Posted: September 6th, 2010, 10:37am MDT by Jérôme Muffat-Méridol (Intel)
(note: this is slide 6 of the nulstein plog)

I hear that the last slide was a bit of a cliffhanger, sorry for having kept the wait so long: I was trying to make a video to attach to this page and I just can't seem to get it right (feels a bit like not being able to spell AC/DC, I must say). I thought I should just move on and ask you to kindly go and download the binaries from the nulstein page instead.

As a matter of fact, I didn't do a much better job of presenting this demo in Cologne... I used a Core i7 980X, six hyperthreaded cores, fitted with an ATI 5870: I should have expected that connecting it to a 1024x768 projector would be akin to bringing a big double-action six-shooter loaded with dumdums to a fun fair stall... GPU was left with nothing much to do, and it became really difficult to make a clear demo out of this...

Let's try again!

In the binaries archive, there is a bin directory with two subdirectories:
- Win32.DX11.Release: contains a 32bits executable that uses demoscene tricks to remain small (using farbrausch's kkrunchy, it packs under 32K, which isn't magnificent but is cool still)
- x64.DX11.Release: contains 64bits binaries without tricks, ie more like what you'd find in a video-game
Pick the executable you want, they do the same thing ; there might be a slight advantage to the 32bits version as it doesn't depend on any DLL and can run straight from the archive. You will see a bunch of cubes, I'll spare you the counting: there are 4096 of them. There are also 4098 point lights, two of them are static and wide-ranged to give some basic lighting to the scene, the 4096 remaining ones have got short ranges, are brightly coloured and each follows a corner of a different cube. They illustrate a classic dependency case: the position of a light cannot be updated until we know the position+orientation of its parent cube, this is the same kind of situation you find in a racing game where the camera wants to be placed at a given position+orientation relative to a car. These lights also jump from one cube to another on a regular basis, flying on their own for a while. This is meant to illustrate the fact that dependencies in games never last forever and will change.

The lights are also coming from an important choice of rendering method: I wanted to see how DX11 deferred contexts would deal with code that would need several passes. So I thought deferred shading would do just that: cubes would go to a GBuffer, and lights would make pixels visible... The only problem is we now have deferred contexts and deferred shading, which is bound to create confusion. I guess "deferred" appeals to coders, alongside JustInTime, because we keep postponing things and always struggle to explain why it can actually be the right thing to do... I know, I'm digressing again, and we're not making progress.

So, you have spinning cubes and rotating lights. Press 'U' and you'll get invaded by UFOs on top, that's another 4096 objects, they fly forward avoiding cubes and do a 180 turn when they come near the end of the "playzone". The original idea was to have them fight each other, but as we'll see a little later I came into a bit of a fistyfight with DX11 before getting the performance I expected, and that ate my time budget. Next time...

And now, for the real question: "what about performances ?"
- run nulstein
- press F1, this shows the information console. You'll see the frame-rate (averaged over 16 frames and over 128) and also the number of threads in use.
- press 'V' to disable VSync
- press 'W' to enable dummy work
- press the Up arrow until the frame rate (just) starts to drop
What is this dummy work? Each rotating cube has a loop during its update (ie the place where CPU cycles are actually useful to the game), doing a cosinus per iteration. If your Dummy Work count is 4096, then each cube is doing 4096 cos ops (ie 16M cos ops in total). This works like a tare, when frame rate just starts to drop, then you are becoming CPU bound.

You can change the number of physical threads in use with the keys '1'..'0' (above characters, not numpad), with '0' meaning 'all'.
Change the amount of dummy work, by using the Up/Down arrows.

On my computer (Core i7 980X, 3.33GHz, ATI 5870, at 1920x1200), I get these numbers before frame rate starts to be affected:
- 12 threads: around 4000
- 6 threads: around 3500
- 4 threads: around 1200
- 2 threads: around 400
This is a very approximate way to measure how much additional CPU muscle is made available, but it gives an idea of how much more work each entity-behaviour can get done in a single frame.

So, what numbers do you get?

Next time, a bit of history before diving in details : to be continued
Spoiler (slides+source code): here
P2P Hopping Protocol

Posted: September 5th, 2010, 1:58pm MDT by Ylian Saint-hilaire (Intel)

In the last week, I started working on the last big missing infrastructure piece of the mesh networking peer-to-peer network. A way to send messages between may two nodes in the peer-to-peer network. Each node communicates with at most 20 neighboring nodes, this is useful to form a mesh, but it only gets interesting is you can route messages by hopping from node to node. Now, each node's identifier is a long hash of the nodes public certificate.

A key question is how do your route over a peer-to-peer network a message from one node to another with only the hash of the source and target nodes. None of the nodes have a general routing table or a full view of the network topology. Still, we can route the message from hop-to-hop by, at each hop, reducing the "distance" between the message and its destination. The distance is measured not is physical or network distance, but in the difference between a node identifier and the target of the message. In any case, it works quite well.

One great thing about this system is that you can message nodes that are behind a firewall or proxy, and it will still be routed correctly. There are plenty of interesting application, notably you can do lots of outside-in scenarios with you access your home computers from a cellphone anywhere in the world.

This week, I will keep working on this system and add replay-detection and message signing and encryption. Should be fun.

By the way, only one week to go before I take up and head to IDF. Lots of excitement to come.

Ylian
meshcentral.homeip.net
Parallelism Education and the Role of Abstraction

Posted: September 3rd, 2010, 2:56pm MDT by Michael McCool (Intel)

On September 13th I will be participating in a panel at IDF on how the shift to parallelism will, or should, affect computer science education. My opinion is that this is a huge challenge, but one that can be met. However, it will require rethinking certain aspects of the CS curriculum, from how (and what) algorithms and data structures are introduced, to what languages are used. It is also worthwhile contemplating how and when the physical design of computers is covered, and what the role of abstraction should be---and which abstractions are appropriate.

Parallelism makes it even more difficult to write correct programs, let alone programs that perform well. However, it is vital that parallel programming be included as part of the CS curriculum broadly. This has to be done in a way that does not neglect core skills, and that ultimately enables students to create reliable, maintainable, and efficient applications.

Ultimately, the goal of CS education should be to instill in students accurate conceptual models of how programs will behave on physical computing machines, along with strong abstraction and design skills that will allow them to efficiently develop usable and efficient software for these machines. The real challenge is going to be one of balance: in a pragmatic sense, how can parallelism be covered in the limited time available for an undergraduate education? How can the necessary new concepts be covered, without sacrificing other crucial aspects of that education? What should the balance be between practical skills useful immediately and underlying concepts useful in the long run? What emphasis should be placed on performance and efficiency?

I personally feel that efficiency is important: if you don’t care about efficiency or performance, then you don’t have to care about parallelism. However, most applications of parallelism, from virtualization to high performance computing, are about achieving as much as possible with a given amount of hardware and power. Of course, this desire for execution efficiency needs to be balanced with productivity: the need to minimize development time. However, software developers (and their managers…) need to realize that unnecessarily inefficient programs are, in fact, environmental hazards, and result in extra costs, and possibly missed business opportunities. Is there a way to achieve both performance and productivity? I believe so---though the intelligent and informed use of appropriate abstractions.

In order to achieve performance, students need to have a clear understanding of the underlying hardware mechanisms in the computer architecture, and in particular what assumptions the hardware is making about programs to achieve performance. In order to achieve reliability and to construct reliable parallel programs efficiently, software developers also need to have a knowledge of good practices for constructing efficient parallel programs, as well as a practical knowledge of the tools.

These goals are complementary, not contradictory, if it is understood that the properties that the hardware requires from programs to achieve performance are relatively simple: data locality and latent parallelism, at multiple levels. Best practices, in turn, can be encapsulated in appropriate design patterns. Design patterns can be taught that have the properties of parallelism and locality, and case studies can show how they work in practice. Software developers with a good conceptual model of the hardware (and the compilers and other systems that map programs onto that hardware) can then use these abstractions intelligently to architect efficient programs.

To be an efficient software developer, one needs to use abstractions. It is not possible to code everything at the lowest level, all the time. Programming languages were invented for a reason. However, abstractions are often taught as a way to “hide information”. This is not quite right. My opinion is that abstractions should be taught as a way to automate and delegate the management of details. However, a good software engineer should, in theory, be able to understand the details, and use that knowledge to guide the selection of appropriate abstractions. “Information hiding” should not extend to a professional’s education.

As for tools and languages: these are still evolving, but what strikes me most is not the variety of parallel programming models available, but how often they are based on a common set of core design principles.

So, in my opinion, a curriculum based around appropriate and well-structured design patterns at multiple levels of abstraction, motivated by real applications and case studies of real system, can achieve the desired goal: software developers who can efficiently create sophisticated, scalable, and reliable parallel applications, and whose skills can evolve along with the technology.
Brace for Test Impact

Posted: September 3rd, 2010, 11:52am MDT by Robert Zych (Intel)

What is Test Impact Analysis?
Test Impact Analysis is a new feature in Visual Studio 2010 (Ultimate and Premium editions) that allows Developers to identify and focus on tests that are affected by specific code changes.

When to use Test Impact Analysis?
Test Impact Analysis eases the maintenance of a large test suite when making many code changes. By detecting code changes and reporting impacted tests, the Developer can focus on maintaining the relevant impacted tests. Time spent re-running irrelevant tests, and the possibility of neglecting relevant tests are both greatly reduced.

How to use Test Impact Analysis?

This simple solution contains a library project and a test project. As you can see from the screenshot above, the Test Results window shows 1 passing test, Add_PostiveInts_ReturnsSum.

The Test Impact View provides access to all the information and functionality that has been introduced with Test Impact Analysis. This view can be loaded by navigating to Test > Windows > Test Impact View. The screenshot above shows the Test Impact View in its initial disabled state. Clicking the “Enable the test impact diagnostics data adapter in the active test settings” link will configure the test settings to capture test impact analysis data.

The “Data and Diagnostics” page not only shows that Test Impact has been enabled, but that many more features are available. Once enabled, a rebuild is required to seed data into the Test Impact View.

Right-clicking on the Add method and selecting “Show Calling Tests” from the context menu updates the Test Impact View to report all the tests that exercise the Add method. In this simple scenario Test Impact Analysis has successfully discovered the relationship between Add and Add_PositiveInts_ReturnsSum.

Changing Add and rebuilding the library has triggered Test Impact Analysis to detect a code change. The Test Impact View is now reporting that Add has changed and is also reporting that Add_PositiveInts_ReturnsSum should be refreshed. Refreshing the impacted tests can be done by simply pressing CTRL+R, Y which is a new shortcut that corresponds to the Run All Impacted Tests command. This command can also be accessed by navigating to Test > Run > All Impacted Tests.

References
How to: Identify the Test Impact of Code Changes During Development
Identifying Code Change Impact on Tests
Intel(r) vPro developers: What do YOU want to emulate?

Posted: September 3rd, 2010, 11:44am MDT by Gael Holmes Hofemeier (Intel)
Many developers know that we used to provide an emulator for Intel(r) Active Management Technology inside our Software Developer Toolkit. Unfortunately, we stopped including it and this was not good news to a lot of our developers.

So why would anyone need an emulator for Intel(R) AMT? Well there are quite a few reasons. I think (and correct me if I'm wrong) companies that are located in other geographies and who wish to build Management Consoles may have the greatest need for a way to test their software without actually having hardware. From my understanding it is difficult for them to get vPro systems, even after they have been launched. I have also heard that there are large tariffs on these systems as well so buying them is often prohibitive. How wonderful would it be for these companies to be able to test their software even though they are not able to access systems?

I'm sure an emulator would benefit many other Software Vendors as well, even if they are here in the US. We would like to hear from our Community. We want to know a couple things:
- Do you have a need for an Intel AMT emulator? If so, how critical is this need?
- What do you need an emulator to do? In-band vs Out of Band; what features are most critical for you to test?
- Do you need an emulator for Provisioning your Intel AMT System?
I hope to get tons of comments on this blog. PLEASE tell us what you think, want, need and must have in an emulator!
SIMD Parallism using Array Notation

Posted: September 3rd, 2010, 8:56am MDT by Arch Robison (Intel)
Are you a C or C++ programmer who has ever envied APL or Fortran 90's array expressions? Read on. If you don't know what array expressions are, then you really should read on, to find out what you should have envied. In any case, the envy is over, because Intel Parallel Composer 2011 brings array expressions to C and C++.
Background
A while back I wrote about the Three Layer Cake pattern for parallel programming. The pattern is a way of organizing programs to fully exploit modern multi-core chips. Two of the layers are:
- fork-join: harnesses multiple hardware threads.
- SIMD: harnesses SIMD instructions.
The compiler in Intel Parallel Composer 2011 extends C++ to directly support these two layers. The extensions are called Intel(R) Cilk Plus. They are:
- Cilk notation for specifying fork-join parallelism.
- Array notation for specifying SIMD parallelism.
This blog introduces the array notation, with a Seismic Duck kernel as the example. I'll introduce Cilk notation in another blog. The two notations are independent. Indeed, the array notation is valuable with other threading packages too, such as Threading Building Blocks, or just for writing faster serial code.
Quick Introduction to Array Notation
The array notation extension is reminiscent of APL and Fortran-90 style array expressions. The expression:

a[index:count]

denotes an array section starting at index with count elements. Scalar operations can be used on conformable array sections in an intuitive manner. Operations between scalars and array sections work too; scalar extende in the obvious way (like in APL or Fortran 90). Examples:
```
    z[i:n] = x[i:n];      // Copies x[i..i+n-1] to x[i..i+n-1].
    z[i:n] = 2*x[i+1:n];  // Sets z[i..i+n-1] to twice the corresponding elements in x[i+1..i+n].
    u[i:m][j:n] += 1;     // Increments elements of two-dimensional mxn array section with upper left corner [i][j].
```
Section notation also permits expressions of the form array[index:count:stride], reductions, and shorthands that I will not into here. I'm presenting just enough to pique your interest. To learn more about it, follow this link to the compiler documentation.
Example
I've described in other blogs how seismic wave propagation in Seismic Duck depends on updating a "tile", a small subarray that fits in cache. Here is the scalar code that dominates execution time. It updates a tile with uniform A and B coefficients:
```
    float a = 2*A[iFirst][jFirst];
    float b = B[iFirst][jFirst];
    for( int i=iFirst; i<iLast; ++i ) {
        for( int j=jFirst; j<jLast; ++j ) {
            Vx[i][j] += a*(U[i][j+1]-U[i][j]);
            Vy[i][j] += a*(U[i+1][j]-U[i][j]);
            U[i][j] += b*((Vx[i][j]-Vx[i][j-1])+(Vy[i][j]-Vy[i-1][j]));
        }
}
```
To improve the speed on compilers that did not automatically generate SIMD code from the scalar loops, I wrote the key loops with SSE intrinsics, so that calculations are done four wide instead of one at a time. The resulting code looks like this:
```
    #define CAST(x) (*(__m128*)&(x))        /* for aligned load or store */
    #define LOAD(x) _mm_loadu_ps(&(x))      /* for unaligned load */
    #define ADD _mm_add_ps
    #define MUL _mm_mul_ps
    #define SUB _mm_sub_ps
    ...
    __m128 a = CAST(A[iFirst][jFirst]);
    a = ADD(a,a);
    __m128 b = CAST(B[iFirst][jFirst]);
    for( int i=iFirst; i<iLast; ++i ) {
        for( int j=jFirst; j<jLast; j+=4 ) {
            __m128 u = CAST(U[i][j]);
            CAST(Vx[i][j]) = ADD(CAST(Vx[i][j]),MUL(a,SUB(LOAD(U[i][j+1]),u)));
            CAST(Vy[i][j]) = ADD(CAST(Vy[i][j]),MUL(a,SUB(CAST(U[i+1][j]),u)));
            CAST(U[i][j]) = ADD(u,MUL(b,ADD(SUB(CAST(Vx[i][j]),LOAD(Vx[i][j-1])),SUB(CAST(Vy[i][j]),CAST(Vy[i-1][j])))));
        }
    }
```
The downside of the change is obvious - it's hard to read. And this was a simple case because logic elsewhere guarantees that jLast-jFirst is a multiple of 4. Otherwise, dealing with the extra iterations would have further obfuscated the code.

For this particular example, explicit SSE intrinsics are not actually necessary with a compiler that automatically vectorizes (convert to SIMD instructions). Indeed, recent compilers that I tried seem to be able to do so. (Though one older compiler from 2008 did not.) But I was careful to cater to the optimizer. I declared the arrays Vx, Vy, and U as static file-scope arrays in the source code, not pointers. That's not trendy OO programming, but it lets the compiler easily prove absence of aliasing, and thus absence of loop carried dependences that could thwart vectorization. It's not always practical to cater this way to the optimizer. Furthermore, array notation has its own elegance. So I'll use the kernel as a running example anyway.

The array notation in Intel(R) Cilk Plus lets me state my intent ("SIMD parallelism!") to the compiler more bluntly. Below is an array notation version of the example:
```
   int i = iFirst;
   int j = jFirst;
   size_t m = iLast-iFirst;
   size_t n = jLast-jFirst;
   float a = 2*A[i][j];
   float b = B[i][j];
   Vx[i:m][j:n] += a*(U[i:m][j+1:n]-U[i:m][j:n]);
   Vy[i:m][j:n] += a*(U[i+1:m][j:n]-U[i:m][j:n]);
   U[i:m][j:n] += b*((Vx[i:m][j:n]-Vx[i:m][j-1:n])+(Vy[i:m][j:n]-Vy[i-1:m][j:n]));
```
Compare the last three lines with the forall loops from which the code was derived in another blog:
```
    forall i, j {
        Vx[i][j] += (A[i][j+1]+A[i][j])*(U[i][j+1]-U[i][j]);
        Vy[i][j] += (A[i+1][j]+A[i][j])*(U[i+1][j]-U[i][j]);
    }
    forall i, j {
        U[i][j] += B[i][j]*((Vx[i][j]-Vx[i][j-1]) + (Vy[i][j]-Vy[i-1][j]));
    }
```
The array notation has let me clearly convey the parallel nature of the updates. I had to add the setup of i, j, m, n. But that's an accident of history. Elsewhere the code computes { iFirst, iLast, jFirst, jLast} from the equivalent of {i, j, m, n} because the former simplified writing the C++ for loops. If I adapt the rest of the code to use array notation, then { iFirst, iLast, jFirst, jLast} will disappear and {i,j,m,n} will be setup in their place.

Of course I'm still depending on a clever optimizer to eliminate the temporary subarrays. For example, the subexpression:
```
    a*(U[i:m][j+1:n]-U[i:m][j:n]);
```
conceptually generates two temporary array sections, for the results of - and *. In practice, the Intel compiler is good at eliminating those temporaries. (It's had years of practice doing so for Fortran 90.) But even if some temporary sections remained, the parallelism is still clear. The compiler does not have to deduce parallelism from dependence analysis of serial for loops.

Concise notation is nice, but how about the performance? When compiled by the Intel compiler and run on the Core-2 Quad system in my office, the array notation variant performed faster than my hand-coded SSE. [Your mileage may vary. See optimization disclaimer here.] I dug through the object code to figure out why. It turns out that updating Vx, Vy, and U in separate loops does better than with a single loop. I found out that the hand-coded SSE does as well if changed to use separate loops to update the three arrays. Anyway, I'm happy that the array notation matches the best that I can do by hand for this example.
Summary
The array notation is a concise way to express SIMD parallelism. I'm hoping it catches on with other compilers. In another blog I'll introduce the application of Cilk fork-join parallelism to Seismic Duck.
My favorite PC accessory of 2010 is my Lap Desk!

Posted: September 2nd, 2010, 6:13pm MDT by Matt Ployhar (Intel)

So this may sound a little odd but my favorite PC accessory purchase this year has to be my Lap Desk. (See below Pic). To make a very long story short I used to use a rigid Art Board for years. However; after many years it started getting pretty worn out. Several months’ back I noticed several Lap Desks at my local Barnes & Noble & figured I’d give one a try. (Note: Lap Desks are sold in many venues – typically in stores where books are sold)

I currently love it! I only wish I’d bought one earlier for my laptop. However; this goes far beyond the added convenience of adding the Lap Desk to the mix, but rather what it allows me to do more comfortably. Which all boils down to me being able to use my laptop more feasibly in other areas of the house. For starters: there’s the living room when I’m sitting on the couch or one of the chairs. Also; it enables me to work, or play games, from the comfort of my bed. In the latter scenario I tend to be a night owl and the Lap Desk definitely provides more options when I don’t feel like reading a book or drawing.

So there’s my very random choice for my favorite PC accessory of 2010 thus far.
Intel Threading Challenge 2010: One Down, Three to Go

Posted: August 31st, 2010, 4:15pm MDT by Clay Breshears (Intel)

The first problem in Phase 2 of the 2010 Intel Threading Challenge contest has closed. I'm very pleased that we had over 20 entries across the two problem classes from around the world. Right now the judging staff is preparing to begin compiling and running the enter applications against the chosen data sets.

The biggest change for this contest is the use of the Intel(R) Manycore Testing Lab. The shared platforms allow contestants to have access to hardware and software that is the same as that used by the judges when evaluating the entered codes. Contestants are now able to tune their entries to the exact machine specs rather than having to code "in the dark" and hope that their solution will execute well when the judges test it. For the judges, the hope is that entries will compile and run without any modifications. (In the past, working through differences in systems, libraries used, and compiler versions between the diverse set of development platforms used and the platforms used for scoring took many hours.)

As with previous problems, the clever participants were able to think beyond the scope envisioned by the judges as the problem descriptions were written up. This led to some long discussions clarifications of the original problem intentions within the ISN forums devoted to the problems. We expect it all worked out well enough for all participants. The judges have taken these discussions to heart and, hopefully, have been able to anticipate better the loopholes that might be found in the current and upcoming problems.

Best of luck to those that submitted an entry for this first problem of Phase 2. If you missed the deadline for the first problem, it is not too late to get started. The second problem has been posted and will end at noon (PDT) on 20 SEP 2010. Each problem awards prizes to the top three point total entries and the grand prize will be given to the contestant with the highest combined point total from their top three scoring entries. Go to the Threading Challenge 2010 page for details on the problems and how to enter.
A Sea Change in Computer Science Education

Posted: August 30th, 2010, 5:39pm MDT by Paul Steinberg (Intel)
After decades of sturm und drang over whether or not to include parallelism in the undergraduate computer science curriculum, we can announce definitively that battle is over. Parallelism is here, and it already abides.
Fortunately, we are not left staring into the abyss. Academia, Industry and Developers are cooperating to help define what the new landscape (or seascape) should look like. While the details are still coming into focus, certain aspects now dominate the discussion:
- We should get beyond thinking about teaching “parallel programming” -- it’s all just programming.
- Parallelism must be introduced early into the curriculum - no later than second year, and it must inform all relevant courses.
- New focus must be paid to architecture - but not the same architecture we’ve been teaching for years.
- Design patterns will take on increasing importance.
- Parallel models are no longer in their infancy - some are mature and can be widely adopted.
- Hiring managers are looking for general knowledge of parallelism more than specific tool sets.
- As educators, we must prepare our students to make the decisions that industry demands - the tools, models, and patterns will lead our way forward.
Agree? Disagree? Good.
We’re going to be having a conversation about this at the IDF education panel “Navigating in a Sea of Cores” on Monday, September 13th. We have representatives from industry and from academia on the panel, and expect to have a lively discussion there continuing through lunch afterwards.

http://idfcommunity.intel.com/planner/SessionCatalog.aspx?track=(ACA).

Free passes are available to educators -Enter the code ACAWEB1 when you register.
For those of you who can’t attend, or for those who want to dry-lab the discussion, we’re also going to have a series of blog posts by some of the contributors. We’ll also be adding links to those further discussions here, so you can just check back to keep up to date!
nulstein v2 plog - back to sequential !

Posted: August 30th, 2010, 4:03am MDT by Jérôme Muffat-Méridol (Intel)

(note: this is slide 5 of the nulstein plog)

In an Agatha Christie novel, this slide would really go at the end of the talk, everything would finally get revealed only in the end, leaving the reader to play detective, picking up clues as the story unfolds... But that's not what I want, this slide goes here, like in a good old Columbo episode: you get to see what happened straight away, and we'll go over everything again to understand the details and make everything right again.

Having found the functional decomposition too complex for my taste, I went back a few steps, trying to split the work up along a different edge. At the time, I was looking at Google's map-reduce and also at the Larrabee rendererer, and one thing really struck me then: what Abrash describes can be seen as a system that maps triangles to tiles and then reduces these to bitmaps... And to generalize this: it is okay to break a process in sequential steps, as long as each step exhibits good parallelism.

Isn't that great: sequential is okay, after all!

This lead me to break the update in two parts: a read-only part and a write-only part. When all that gets done is reading, there is no need for locks, everybody can do it at once. When all that gets done is changing own state, again there is no contention possible and no arbitration is required. Of course, there are a few more nuts and bolts required to make this work, but here you have it: split that update in two phases, and everything can get updated in parallel much more easily.

Breaking the draw phase down is quite easy too, collect information about what everything wants to draw, sort that and do the actual render in multiple deferred render-contexts (as provided by DirectX 11). Here, it can almost be seen as straight map-reduce: a set of objects is processed to generate set of intermediate key/value pairs, which gets reduced into a set of command lists, ready to render.

The unexpected part for me, when carrying out development, was that I would still have one thread just talking to DX and very busy doing that. That's the part I was trying to kill and, as it turned out, it did survive and stop being a problem.

There are five slides before we really dive into the details of how this works, which should turn into a couple of weeks worth of blogging, so I'd like to invite everyone who is interested to start playing in their mind with the idea of two-stage update (all read and, later, all write). Look for things that don't look like they should work, look for ways to address those problems, try and see what in your game would stop working if it had to be written like that, and try to think if there would be any way to fix it. That's the great thing about making this talk a plog: you get to really think about what I present while I'm presenting it. The unfortunate thing is that our comments system seems to be down at the moment and we can't interact properly. So, if anybody wants to feedback, feel free, you can twitter @jmuffat or email jerome dot muffat dash meridol at intel dot com.

Next time, demo!
Spoiler (slides+source code): here
Seismic Duck goes Open Source

Posted: August 28th, 2010, 9:42pm MDT by Arch Robison (Intel)
Now you can read the source code for my Seismic Duck game on Source Forge. I open-sourced the code for several reasons:
- My blogs on parallelizing it with SSE and TBB omit details of interest. The blogs chiefly concern the seismic wave propagation code in Source/Wavefield.cpp .
- Games about reflection seismology are not runaway best sellers.
- It's limited to Windows. I'd like to find volunteers to port it to other platforms. Mac OS is of particular interest, since it is common in educational settings. The OS-specific parts are about 600 lines of C++.
The code is my own hobby, not Intel's. As such, comments are sparse. I'll expand them as questions arise. If you are interested in porting it to new platforms, please contact me and I'll help as best I can.
Shopping athletes get new embedded help

Posted: August 28th, 2010, 9:02pm MDT by David Stewart (Intel)
I'm not really big on "shopping" as a sport. Some people love to wander the up and down the aisles of Costco on a "treasure hunt" to see new and unexpected items for sale or wander from store to store in a shopping mall. I'm more one of those "hunters" who targets what I need, goes in for the kill, and relaxes in the cave after the hunt.

But I can see how something like the smart kiosks that Paul Otellini showed off in his Comdex keynote would be cool for shopping athletes. (Spendletes?) In case you missed it the first time around, here it is again:

Here's the link:
[www.youtube.com]

Offhand, if you were given the job to build something like this for a customer, what kind of technology would you need to pull it off?
- 3D graphics. Plenty of animations which would be nicely rendered in OpenGL or it's cousins.
- Touch input with a really big touch screen area.
- Recognition algorithms which can take a video feed and determine the height and gender of the shopper.
- Video playback. You probably want efficient video decode.
- Networking and a quick database connector to look up loyalty memberships
- Blue tooth connection to send directions or coupons to your phone
- How about enough processing horsepower to handle multiple of these kiosks in the store
Although all of these appear to be important, the most critical technology of them all is not even listed here.

The most important technology is that it doesn't crash.

When I see something like this demo, I imagine kids coming into the store and playing around with it endlessly. I see teen hackers trying to break into the network somehow. I see a store staffed with employees who don't have the training to fix it if it goes haywire.

That's why this kind of thing is considered an embedded application. If you deploy something like this in your store, the last thing you want to see is a BIOS setup screen or the Blue Screen of Death. You design it to be tough as a tank and to run forever.

Frankly, this is one reason why people start with systems like an embedded Linux system, which has a great reputation for running for months on end with no intervention even with advanced technologies running on top.

Of course, it's just a short step from this kiosk to the kinds of displays we saw in "Minority Report"

[www.youtube.com]

No telling when people will be willing to give up their privacy for the sake of a better tank top at The Gap.
Testing Intel’s Parallel Studio

Posted: August 27th, 2010, 5:44pm MDT by Guy Tel-Zur

I just published a post at my other blog about Intel's Parallel Studio for OpenMP and MPI applications. My Conclusion is that this tool is useful for OpenMP (and TBB) but not for MPI.
You are welcome to read it from here [telzur.blogspot.com]
Starting from the forthcoming semester I am going to incorporate Intel's Parallel Studio in my Parallel Processing course for demos and for hands on practice during lab sessions.
Have a Cisco ACE XML Gateway? Intel(R) SOA Expressway to the Rescue

Posted: August 27th, 2010, 2:34pm MDT by Blake Dournaee (Intel)

It looks like Cisco has issued both an end-of-sale and end-of-life announcement for their Cisco ACE XML Gateway.

In response, the SOA Expressway team has teed-up a special offer for Cisco customers looking to move to replacement XML Gateway.

This is an interesting development to be sure, and it probably signals that Cisco is seeing less demand for XML traffic than anticipated. Voice and video probably have taken over a larger share.

All this being said, I remember talking to a CTO at a major networking company (not Cisco) about 5 years ago about the proportion of XML traffic as a fraction of total Internet traffic, and while I forgot his name, I can't forget his comment which was something along the lines of: "90% percent of Internet traffic is spam and porn."

I wonder how much the proportion has changed in the last 5 years? Hopefully it is an upward trend :)
Adding web page tooltips that are iPad compatible

Posted: August 27th, 2010, 2:27pm MDT by Ylian Saint-hilaire (Intel)

In recent weeks, I have been working on MeshCentral, a central web site for managing all our computers. I got lots of features added in and more to come but I wanted to make the web site more user friendly by adding pop-up tool tips as certain places. I also wanted it to not be annoying and be compatible with touch screen devices such as the Apple iPad and the many others that are likely to hit the market.

I just started getting familiar with JQuery and looking for JQuery compatible tool tips is easy, there are many of them. In fact, JQuery as basic support already built-in. Sadly, all of these will detect that the mouse hovers over an area and display the help. First, I wanted to have the user click to get help, avoiding having tip windows pop in and out as the mouse moves. I also wanted the tip window to close using a close button. This way, the site would work great for tablet owners.

After some research I found a great example in "atooltip", it did exactly what I wanted but did have some quarks I had to fix. For example: When clicking many tips in a row, the help text would pile up on the window. I also has a problem with my social configuration page. The user on that page can opt to hide portions of the page, and hitting a tool top and closing the area on the page should close the tool tip.

Well, took about two hours but tool tip help support is now added to MeshCentral. I only use it in two pages (account & social settings), but more to come.

Ylian
meshcentral.homeip.net
nulstein v2 plog - divide and surrender

Posted: August 27th, 2010, 10:05am MDT by Jérôme Muffat-Méridol (Intel)

(note: this is slide 4 of the nulstein plog)

I like calling the time when I started writing games "the good old days", it was in the nineties, DOOM's era, I had quit doing IT development work for hire to join a crazy team, doing creative stuff, pushing machines and people to the limits of what they could achieve. Everything felt heroic, there were no ready-made bricks, you'd start from almost scratch every time. As Hervé Lange used to put it: "imagine you're making movies and building the camera is part of the process". It felt good and it feels like long time ago now (it is) and, to be fair, the only thing that's now false in this statement is that you don't have to build the camera any more (but still, you can...)

Back on topic. The sequence of operations in a video game is very straight forward: frame, frame, frame, frame... We keep rendering frames, in a loop, evolving based on the players' inputs and the state of the previous frame (ie "render-farm" style is not the way to go). The work for a frame splits in two main parts: updating game state (advancing time) and drawing it. And inside these parts, we find modules that are loosely connected : collision/physics, AI, audio, scripted mechanisms, visibility/culling, the actual rendering and more... When everything was sequential, it was possible to use the order in which these were processed to make our lives simpler, but order wasn't so critical. So, when CPUs with multiple cores started to appear, the natural thing to try was to split per module and spread work like that. GPUs had been around for a while too, and the idea of a pipeline that would go from one core to the next to then move on to the GPU felt like it made sense.

This approach sorts of work with two cores: one core runs the update side of things, the second deals with drawing things and off everything goes to the GPU. Nice and easy breakdown, data always flowing in the same direction, looks cool on the paper. Until you start tuning... In the really old days when the term "3D accelerator" hadn't even be invented, everything happened on the same chip, it was like juggling with one ball (I can do that). Add a GPU: depending on what you do you might be CPU bound or GPU bound and the optimal use of the machine is to get both to spend about the same amount of time working, you can achieve this by varying the amount of graphics detail, it's as easy as juggling with two balls (I can do that too!). Now, in a pipelined model like I was describing, you want the core that updates the game, the one that draws the frame and the GPU rendering polygons to all spend about the same amount of time working, and I'll call that juggling with three balls (which I can't do, but hope to achieve one day). But then there are four cores, six cores, hyper-threading, and it's clear that pipelining won't work.

The next logical step is to keep the principle of functional decomposition and get rid of the pipeline idea only. Also, because some modules can leverage parallelism internally, like physics that can process islands separately, it becomes possible to spread work a little more easily. Data flow is more complicated but the real difficulty is synchronisation between the various modules. Together with the need to balance work between all cores, this converges to require the engine to split work in ever smaller jobs. The ideal chunk of work being one that executes in a reasonably small amount of time and never needs to wait for any other...

This is how one goes from moving AI to a separate thread, to splitting it in sub-groups, and again until reaching the level of the individual and moving on to split behaviours in separate "aspects". And then only do you finally have jobs that never wait (and are small). Cores can be kept busy and dependencies are implicitly managed by jobs firing as their prerequisites happen. The main difficulty that arises now is complexity, you have to think in terms of objects at a level of granularity below the individual unit (from the player's point of view). The resulting jobs are also likely to end up being so small they become too small and the overhead of managing them starts to weight on performances. Like I said last time: this is hard!

I think the best description available online of a system that works is the one about Dice's Frostbite engine. Slide 26, the CPU job graph looks scary at first and probably isn't that bad but it does illustrate really well both the need for breaking things down in small blocks and for keeping track of dependencies. Slide 29 shows that even in one of the most elaborate engines today, it is unavoidable to have cores going idle waiting for other cores to finish.

But do we have to go down to that level of complexity? In this project, I'm showing an alternative approach that attacks the problem from a different angle. But, this post is already long, you'll have to wait for next time...

Next time we'll see how work is subdivided in nulstein
Spoiler (slides+source code): here
Smart/iPhones – a convergence hub device? I believe so.

Posted: August 26th, 2010, 9:18pm MDT by Matt Ployhar (Intel)

A few days ago I received my iPhone 4 and I absolutely love it! The setup was pretty straightforward and easy to navigate. So far the only thing that took any length of time was the necessary step of downloading iTunes for the device which is primarily used for syncing contacts, email, and the like from my PC. After toying around with this device for a few days and gathering my initial impressions I started pondering the past, present, and likely the future for Smart/iPhones.

Historically speaking my early cell phones progressed from an early MicroTac (1996) to a MPX200 Smartphone (2003). After that I found I pretty much only used the Smartphone for the calendar functionally and sort of gave up on them for awhile and went back to a normal cell phone (Razr). Over the past few years I then moved towards a Pearl blackberry device which I had more success with in leveraging other functionality such as email, texting, etc.

So what fascinates me the most about all of this and what does it have to do with my position statement about Smart/iPhones being a convergence hub device? There are actually several things. Going back over the history of my cell phones I can’t help but notice that the displays in the 90’s have transitioned from 2D LED’s to the gorgeous touch capable 2D/3D LCD’s that we see today. Furthermore; when you look under the hood at the capabilities of something like an iPhone 4 its literally about twice as powerful as the first desktop PC I purchased which was a Micron P266 with an 8mb video card! Throw in a 5-12 MPix camera and portable Music/Media players (e.g. Walkman, iPod), and I believe there’s been some significant convergence going on in the handheld space.

Given that the capabilities of Smart/iPhones are currently accelerating at a Moore’s law pace or faster; where do they go next? My prediction is that they likely won’t replace PCs (Laptops/Desktops) but will end up being a central “Hub-like” device that enhances one’s existing PCs and other Smart Devices. If past trends are any indication of the future then it’s not out of the realm of possibility that in the next five to ten years Smart/iPhones become more important as they become glorified memory sticks (Hard Drives) tethered to the cloud, keeping your data synchronized. I expect that they’ll end up with processors in the 2-3+ GHz range, with Drive capacities in the range of 100-250GBs or more, and sporting video graphics capable of handling DirectX11/OpenGL 4 games & applications. When we add the additional ability of these devices being able to push or pull wireless HDMI, WiGig, etc types of signals to the mix I foresee some interesting game changing scenarios emerging. At least I hope we’re heading in this direction! In the meantime I’m going to go download some games for my new phone!
Life, the game (you and Scott Pilgrim vs. the world)

Posted: August 26th, 2010, 4:26pm MDT by Scott Crabtree (Intel)

As a game designer and developer I know the power of points. Even if they have no connection to the real world, it feels great to score points, and even better to score big points, and level up.

In case you haven't noticed, the rest of the world is catching on. For years we've been earning points (miles) in frequent flier programs, which have of course expanded into all kinds of frequent buyer programs (your 11th haircut is free). As Jesse Schell's DICE talk

read more
My Lab's Computer Power State Now Public

Posted: August 26th, 2010, 4:25pm MDT by Ylian Saint-hilaire (Intel)

Today I added a new feature in MeshCentral that allows an administrator to make some of the state of their computers public for anyone to see. Obviously, this is not enabled by default, but when enabled MeshCentral gives you a link to a publicly accessible web page you can share with anyone. Now your friends can see the power state of your computers at any give time., great if you want to share this on social networks. By the way, if you opt to make the information public and also setup Twitter, a link will be added to each Tweet. So, if a computer just turned off, you will see a message like "Contact lost with ComputerX" followed by a link to the public information about ComputerX.

At Intel, I have a lab with a bunch of machines and I am making their power states public for everyone to see. The link is: [meshcentral.homeip.net] . I also am making the mesh "graph" viewable by the public, so you will see a link to the graph showing the connections between the nodes in my lab. None of my lab's computers move much, so there is not much chance of seeing anything other than a fully connected graph, we may get more interesting graphs as I add more computers.

By the way, I added OpenID support for Google and Yahoo yesterday, seems to work pretty well.

Ylian
meshcentral.homeip.net
Unity as a multi-platform development environment.

Posted: August 26th, 2010, 2:49pm MDT by Code-Monkeys

window.fbAsyncInit = function() { FB.init({appId: 'your app id', status: true, cookie: true, xfbml: true}); }; (function() { var e = document.createElement('script'); e.async = true; e.src = document.location.protocol + '//connect.facebook.net/en_US/all.js'; document.getElementById('fb-root').appendChild(e); }());

Tweet //

To all the folks here who are looking at game creation on AppUp (or elsewhere) we wanted to share our recent experience with the Unity Game Engine.
We'll show a little video here but in short: UNITY ROCKS!

read more
Unity as a multi-platform development environment.

Posted: August 26th, 2010, 2:49pm MDT by Code-Monkeys

window.fbAsyncInit = function() { FB.init({appId: 'your app id', status: true, cookie: true, xfbml: true}); }; (function() { var e = document.createElement('script'); e.async = true; e.src = document.location.protocol + '//connect.facebook.net/en_US/all.js'; document.getElementById('fb-root').appendChild(e); }());

Tweet //

To all the folks here who are looking at game creation on AppUp (or elsewhere) we wanted to share our recent experience with the Unity Game Engine.
We'll show a little video here but in short: UNITY ROCKS!

read more
Presenting at IDF, September 13-15th

Posted: August 25th, 2010, 11:40pm MDT by Ylian Saint-hilaire (Intel)

It's official. I will be a speaker at IDF in San Francisco September 13th to the 15th. It's coming up very soon. Today we had another review of the presentation material. Most speakers have finely tuned decks of slides, just like I do. But when starting the review I say that I will not be presenting many of the slides. Instead, I opt to do hands-on demonstrations throughout the presentation. It's must fun and the autience gets a feel of the technology instead of the slides. I hope you will join me.

I will be giving two, 2 hours labs on the first day labeled "PROL001" and "PROL002". These labs will review the basics and the latest Intel AMT features. I show you how you get to impress your friends with some computer magic and Intel AMT. The second part of the labs will be focused on cloud computing. Web services like GMail, Hotmail, Facebook are the hot new thing. Seems like you should be able to manage your computers like to do online mail. I will be talking about how Intel platforms are the best clients for cloud computing and how you can connect platforms to cloud services using peer-to-peer networks.

Like the first half of the lab, I expect the second half to be all hand-on. Showing off how you can power on and off computers from a iPod Touch, or get the state of computers on Twitter.

On the 3rd day, I will be presenting a 50 minute session "SOLS004". This session will focus entirely of peer-to-peer cloud computing.

Hope you can join us at IDF!

Ylian
[opentools.homeip.net]
Started work on OpenID / OpenSocial support

Posted: August 25th, 2010, 9:48am MDT by Ylian Saint-hilaire (Intel)

We are hard at work building new features of the MeshCentral web site. In the last week, we started work on two more features that are high on the list. First, OpenID. It's insane to think that web users will create one more account in MeshCentral to manage a few computers when they already have web accounts all over the place. OpenID will let you log into MeshCentral using your Google or Yahoo account and you don't have any password to remember. In fact, if you are already logged into Google, users are two clicks away from having a presence on MeshCentral. I have been using DotNetOpenID in my ASP.NET server to add OpenID support and last night it worked for the first time.

Well, OpenID is all well and good, but before this new feature makes it into the production server, I need to also add the feature to Mesh Connector, the little tool that creates mesh networks and links the mesh to the web account. All of the Mesh tools will need to have OpenID support too.

Another feature we are working on is Open Social. This allows us to build a gadget that can be inserted into other sites like iGoogle or Linkedin. The idea there is to make logging into MeshCentral seamless as possible. Most of the time, we want to just get an overview of the power use and location of our computers but nothing more. A gadget can do that very well. If you need more, the gadget can provide a link to the site for more management options.

In addition to OpenID and OpenSocial, we are working on improvement in our Twitter support. That should be coming up in the next couple weeks.

Ylian
meshcentral.homeip.net
nulstein v2 plog - parallelism, not quite there yet

Posted: August 25th, 2010, 7:23am MDT by Jérôme Muffat-Méridol (Intel)

(note: this is slide 3 of the nulstein plog)

Last time, we saw how hardware is now all multicore, today we're looking at the software side of things, parallelism in video-games. The short story is that despite an impressive amount of effort, games currently don't get as much benefit from multicore as other types of applications (like Digital Content Creation, for example). And it's not just because games are often GPU bound, the available CPU cycles could be used for more complex animation, more interesting ambient AIs, better culling, all sorts of features that could make the games look better without drawing anything more or changing the gameplay. We rarely see these and I believe the main reason why we aren't exactly there yet is simply because it is so hard to parallelize a game.

Making a game engine parallel is a hard task. Games are all about everything potentially interacting with anything else, not only do we have objects that exhibit a large amount of dependencies, these dependencies continually change as the game evolves. In unpredictable ways, too. This would already be well complicated, but it is also important to realise that there are many types of dependencies and interactions: the interaction between a bullet and what it hits is different depending whether it is a bottle, the wall, a civilian, a guard or the player. And the variety of these interactions is key to how rich the game will look. From a coding perspective, we have a large amount of tiny little tasks, which sounds good for parallelism until you realise they're all interconnected like an entangled mess of neurons and dendrites, animating... But who said coding a game is simple? Several consoles come to mind, to illustrate coding games is hard, and that's never stopped anybody. So, yes, coding a game to be parallel is hard, but that's business as usual.

Say we have an engine, the next thing that becomes harder with parallelism is debugging and tuning. Trying printf debugging on parallel code is fun, but hopeless. Something as simple as setting a breakpoint to understand context usually leads to more questions than answers. Very often it all ends up in a situation where the observer modifies the experiment. And that's just about looking at the kind of bugs you would normally find in classic sequential code, but we also have a whole new category of problems related to simultaneous operation. Deadlocks are a bit like crashes, they're ugly but you know when you have one. Race conditions can be so elusive, they might not be seen during development. Beyond bugs, the impact of locks on performance can be enormous and tremendously hard to picture, the easiest way to describe the difficulty of the task is to think about organising roundabouts, priorities and traffic lights in a city (can't help but remember my days in London)... It's hard, lots of effects, lots of side-effects, in cascade. But again, in games, that's business as usual...

Ok, say we have an engine and it works and it's fast, are we done? Actually we aren't, we're just getting started: now, we're going to give it to a team, to make a game, and they're going to push it to its limit, beyond its limits, make it scream and create the best game there is now (which hopefully will still be good enough by the time it is out). And here again, we face something that is hard: train the team in being parallelism-friendly. And I believe it is the #1 reason why it is so hard to reach good concurrency in games. As I said above, there are many individual behaviours and even more interaction types, they all require code and that code isn't going to be written by engine programmers. Some isn't even written in C but relies on some scripting language (often engine specific although I hear LUA is getting quite a bit of traction). With a parallel game engine all coders, from the glorious engine wizard to the lowly scripting peon, must deal with their code running in parallel with something else and worry about concurrent access to data. This is scary, or put another way:

That engine better be simple, really simple.

And that's where it's not business as usual. Normally, your engine programmers would be encapsulating all the complicated technology stuff and hide it behind a friendly KillerGameAPI that abstracts the bits you don't really want to know about on a day to day basis, and they would only be called upon in the localised cases where awareness of the details matters. Here, we need to take this very complicated and dangerous paradigm and somehow turn it into something that is reasonably safe, as efficient as we can and that everybody can feel confident they understand... All at once...

I think that's what's really hard.

nulstein tries to be such a simple engine: a few simple rules, a minimal need for locks and the ability to spread work over as many cores as are available.
So hard, yes, impossible : no.

Next time we'll have a first try at dividing the work
Spoiler (slides+source code): here
Why Embedded has become cool (again)

Posted: August 23rd, 2010, 6:16pm MDT by David Stewart (Intel)

When journalists or pundits consider the impact of the computer, they wax poetic about how today's smart phone has as much processing power as the mainframe computer of the 1970s.

It makes me giggle to think of running the 1970 US census through my Google Nexus One. But the real impact of computing on our lives is in embedded computing. And it's about to get a whole lot bigger.

Just think about it - when was the last time you used a physical key to open a hotel room door instead of one of those little mag strip cards? (Just last weekend for me - I stayed in a B&B, but you get the point). Maybe you have noticed that in cities from Prague to Portland that coin-operated parking meters are disappearing in favor of machines that take a credit card. And listening to music in some form other than digital (or live) is becoming a museum curiosity.

This is the world of embedded computing. And there is an automation revolution in areas as diverse as medicine, telecommunications, retail and casino gaming.

Now I have to admit that for a long time when someone would talk with me about embedded computing, I would consider this the domain of wireheads and electrical engineers stringing together components with very little software.

But with 32 bit microprocessors now at a very attractive price point, the processing power available for embedded computing just became very interesting.

Just think about those parking meters I mentioned in Portland and Prague. They are solar powered, can read your credit card and communicate with the payment network to authorize the payment. What else could this machine do? Well for one thing, it could talk on the cell network. Dan Hesse, CEO of Sprint gave an interview recently in which he said:

"Then there's what I call the inanimate objects that will start to carry wireless chips...what we call machine to machine. Meters will be read, vending machines... you go right down the list. Cars will have wireless chips where they are monitored all the time. And that will give us revenue on our part so there will be many more devices that are connected to the wireless network than there are people..."

This machine to machine (or M2M as it's known in the lingo) will definitely drive the desire for more compute power. Think about what a city government could do with a downtown area full of connected, intelligent devices standing literally on every street corner. They could monitor for fire, gas leaks, crime, all kinds of things. It's almost like having a cop on every corner. (And I'm sure there are plenty of potential privacy concerns here as well).

So I'm starting to get much more interested in embedded computing, as the opportunities for cool software become more tangible as better processors get out there. I like to solve problems, so I'm looking more at what we can do to take advantage of that cool processing power with phenomenal software.
Tomorrow starts here. Intel Developer Forum.

Posted: August 23rd, 2010, 1:24pm MDT by Rick Puckett (Intel)

The Intel Developer Forum (IDF), September 13-15, 2010 in San Francisco, is where visionaries gather to share ideas on the future and experience the latest developments in IT, cloud computing, mobile computing, software, and visual computing. At IDF you’ll hear from Intel engineers and industry leaders, and get critical technical training. Register now.
Come join us!
Why AppUp? - A Quick Review of the AppUp Model

Posted: August 23rd, 2010, 11:58am MDT by Bob Duffy (Intel)

Intel launched a beta version of its AppUp Center online store in January of 2010. Under the beta program developers have known AppUp as a single store front primarily supporting netbook applications developed in C/C++. Unfortunately this history does not put the overall value of AppUp in proper context. Here's a look back and forward to help you know what to expect with AppUp.
read more
nulstein v2 plog - now is multicore

Posted: August 23rd, 2010, 7:16am MDT by Jérôme Muffat-Méridol (Intel)

(note: this is slide 2 of the nulstein plog)

You've been hearing us (at Intel and elsewhere) say "the future is multicore" for a few years already, and what this excerpt from the Steam Hardware Survey tells us is that the present is multicore too. It's always difficult to pick a stat that everybody will agree on, but I think this one is particularly fitting: why would you install Steam if you're not (at least) contemplating the purchase of a game? So, this doesn't just focus on machines used to play games, it also focuses on people who actually are willing to pay for them. I believe this makes the stat interesting, even if it represents only a subset of the population we're interested in (my assumption being that it is a representative subset).

It says that a game bought today is 55% likely to be played on a dual core processor, 27% on a quad-core and 15% on single core (I believe hyperthreading is not taken into account as my Core i7-980Xgets reported as having 6 physical processors).This survey also shows that the quad-cores have taken second place and overtaken single-core systems around the end of 2009, so really there is no question that you can count on a significant installed base of machines able to run 4+ threads simultaneously, today. And it will just go on from there and keep growing.

So, if the future is already there, what's the next future, then?

On the one hand, we'll have more of what we've always seen: things grow smaller. And smaller again. What we're seeing with Atom(tm), the success of slim netbooks with 10+ hours of everyday-stuff computing power, is a clear indicator that not only is the technology here but that it's also something a great deal of people want. Moore's law is at work here, again, and these chips will keep shrinking while becoming more powerful. One obvious reason why multicore is a key way to make these more powerful is that when they're not doing much, we can start shutting down cores, saving precious energy very effectively. The future of small is definitely multicore.

On the other hand of the spectrum you have initiatives like Intel® Many Integrated Core (MIC) architecture, where hundreds of physical threads run simultaneously and still manage to retain a shared-memory architecture. Absolutely no surprise here: whether it is handfuls of threads in the main processor or scores of them on a coprocessor-style card, the future of big is multicore or, rather, manycore.

I think that summarizes where we are on the hardware side of parallelism and there should be no doubt that, wherever you're looking at, the best way to take maximum advantage of the CPU is parallel code.

Next time we look at the software side of things: to be continued
Spoiler (slides+source code): here
Integration of Altova's MapForce Data Mappings Into SOA Expressway

Posted: August 22nd, 2010, 8:06pm MDT by Joe Welsh (Intel)

Altova is well known for it's flagship product XMLSpy - as anyone who has worked extensively with XML data can tell you. However, they have an entire suite of product offerings, one of which is MapForce. As described on it's website:

"Altova MapForce® 2010 is an award-winning any-to-any graphical data mapping, conversion, and integration tool that maps data between any combination of XML, database, flat file, EDI, Excel 2007+, XBRL, and/or Web service, then transforms data instantly or autogenerates royalty-free data integration code for the execution of recurrent conversions."

In case you weren't aware, SOA Expressway is remarkably extensible. In this post I will share with you my experience integrating MapForce's data mapping projects into SOA Expressway.

Use Case

Suppose there is a need to integrate legacy flat file delimited data into a web services orchestration within SOA Expressway. Since web services utilize XML for its payload, the legacy data needs to be converted to XML. Although SOA Expressway's Data Transformation services could easily transform the legacy data into XML required by web services, a MapForce data mapping project already exists that easily handles this XML conversion.

Because MapForce allows it's projects to be exported to external executable code, these data mapping projects don't necessarily have to be redeveloped by another integration appliance to be utilized by that appliance.

Using this feature to export Java code, MapForce data conversions can be directly integrated into SOA Expressway. SOA Expressway's Java Extensibility Guide (included in the product) outlines how to incorporate this code to build a customized "data-mapper".

Exporting the "data-mapper" to a Java plugin allows any application with SOA Expressway to utilize it.

Comments

This use case provides another demonstration of SOA Expressway working along side with other integration appliances. Even though SOA Expressway has the tools to directly work with legacy data and protocols, it is nice to know how easy extensible it is. MapForce is a solid product with a rich feature set. I found the Java code generated by MapForce very thorough, flexible (allowing for a variety of input and output formats), well commented, and with plenty of error and logging capability.

Interested in trying this out? You can download a 30-day evaluation of SOA Expressway from www.dynamicperimeter.com/download/SOAExpressway and if necessary an evaluation copy of MapForce from Altova's website.
Nothing but "Net" - book - Four days so far - On vacation with a Netbook and AppUp

Posted: August 20th, 2010, 4:05pm MDT by Russ Beutler

So far four days with only my netbook. I have had the chance to download apps from the AppUp Center and use them as I have been attending courses at Education Week - A continuing education program with my Alma Mater. The applications I have used so far include: Newsy, My Little Artist for doodling, aClock for a clock I can see, Yoono to keep in touch with my family and friends, as well as Alchemy Classic, Ancient Frog and Country Connect for games.
read more
Nothing but "Net" - book - Four days so far - On vacation with a Netbook and AppUp

Posted: August 20th, 2010, 4:05pm MDT by Russ Beutler

So far four days with only my netbook. I have had the chance to download apps from the AppUp Center and use them as I have been attending courses at Education Week - A continuing education program with my Alma Mater. The applications I have used so far include: Newsy, My Little Artist for doodling, aClock for a clock I can see, Yoono to keep in touch with my family and friends, as well as Alchemy Classic, Ancient Frog and Country Connect for games.
read more
Parallel Programming Talk #89 - Prof. Alexandra Fedorova on Managing Contention for the Shared Resources on Multicore Processors

Posted: August 20th, 2010, 12:19pm MDT by Aaron Tersteeg (Intel)

Enclosure: [download]

Welcome to Parallel Programming Talk #89. On the August 10th episode Clay and Aaron talked with Prof. Alexandra Fedorova about Managing Contention for the Shared Resources on Multicore Processors.

Download Link - MP3 Audio File (Small):
Download Link - High Quality MP4 Video File (Large):
First the News:
Threading Challenge Phase 2 Problem 1 began on Monday, August 9, and is due 2010 August 30, 2010 at 12:00 PM (Pacific Daylight Time).

Get ready to attend the CT Tutorial to be given by Intel’s Dr. Michael Klemm, at the Nineteenth International Conference on Parallel Architectures and Compilation Techniques (PACT) September 11-15, 2010 in Vienna Austria. Registration for the conference is well underway and you can even register the week of the conference.

Superscalar Programming 101 (Matrix). For this 5-part article, ISN Black Belt Jim Dempsey takes a small, well-known algorithm, shows a common approach to parallelizing that algorithm, follows with a better one and lastly, produces a fully cache-sensitized approach. Readers of this article will learn a methodology for interpreting test run statistics and to improve their code using those interpretations.

Intel Developer Forum Returns to San Francisco, Sept. 13-15

SC10 - The Super Computing Conference is being held November 13-19, 2010 in New Orleans.

If you have questions you'd like to see up discuss, ideas for show topics or just want to send fan mail.... Send Email to parallelprogrammingtalk@intel.com

On Today's Show:
Dr. Alexandra Fedorova, Assistant Professor, School of Computing Science, Simon Fraser University

Dr. Fedorova leads the Systems Research Group at SFU, which is a part of the SyNAr (Systems, Networking and Architecture) lab that she co-founded. Her research focuses on system design for multicore processors and on parallel computing.

On the show Dr. Fedorova discussed her paper "Managing Contention for Shared Resources on Multicore Processors" that she co authored with Sergey Blagodurov, Sergey Zhuravlev; Simon Fraser University. The paper presents research showing that  contention for caches, memory controllers, and interconnects can be alleviated by contention-aware scheduling algorithms.

From the paper, "Modern multicore systems are designed to allow clusters of cores to share various hardware structures, such as LLCs (last-level caches; for example, L2 or L3), memory controllers, and interconnects, as well as prefetching hardware. We refer to these resource-sharing clusters as memory domains, because the shared resources mostly have to do with the memory hierarchy. Figure 1 provides an illustration of a system with two memory domains and two cores per domain.

Threads running on cores in the same memory domain may compete for the shared resources, and this contention can significantly degrade their performance relative to what they could achieve running in a contention-free environment. Consider an example demonstrating how contention for shared resources can affect application performance. In this example, four applications—Soplex, Sphinx, Gamess, and Namd, from the SPEC (Standard Performance Evaluation Corporation) CPU 2006 benchmark suite6—run simultaneously on an Intel Quad-Core Xeon system similar to the one depicted in figure 1.

As a test, we ran this group of applications several times, on three different schedules, each time with two different pairings sharing a memory domain. The three pairing permutations afforded each application an opportunity to run with each of the other three applications within the same memory domain:

1. Soplex and Sphinx ran in a memory domain, while Gamess and Namd shared another memory domain.

2. Sphinx was paired with Gamess, while Soplex shared a domain with Namd.

3. Sphinx was paired with Namd, while Soplex ran in the same domain with Gamess.

Figure 2 contrasts the best performance of each application with its worst performance. The performance levels are indicated in terms of the percentage of degradation from solo execution time (when the application ran alone on the system), meaning that the lower the numbers, the better the performance."

Dr. Fedorova was awarded a Google research award to address the issues of power consumption and efficiency in data centers. Data centers are becoming an increasingly important part of the world-wide computing infrastructure. They offer a promise of scalability, reliability and manageability for the ever-more prevalent online services. The problem is that data centers consume inordinate amounts of power: over 7.2 billion dollars is spent every year on energy consumption in US data centers alone.

Dr. Fedorova and her students have been designing innovative solutions to improve energy efficiency of virtual machine technology (a key technology for data centers) and to enable the software to use modern multicore hardware more effectively. The research award from Google is a way of recognizing the importance of this work.

Coming up next on Parallel Programming Talk...
Introducing Kathy Farrel the new Parallel Programming Community Manager
Date/Time: 8/24/2010 at 8:00 AM Pacific - Watch Live on Intel Software Network TV

Set your alarm to watch Parallel Programming Talk every other Tuesday at 8:00AM PT.
Parallel Programming Talk #88- Listener Question Show

Posted: August 20th, 2010, 11:48am MDT by Aaron Tersteeg (Intel)

Enclosure: [download]

Today is August 3th and on show 88 Clay and I will be Answering Listener Questions with 1.21 Gigawatts of power running through our flux capacitor!
Download Link - MP3 Audio File (Small):
Download Link - High Quality MP4 Video File (Large):

First the News:

Congratulations to Our Threading Challenge Phase 1 Problem 2 winners!
Master Level: 2 - Skip List - 1st Place: Dmitriy Vyukov
Apprentice Level: 2 - Prime Array - 1st Place: doraemonok
Phase 2 Problem 1 began on Monday, August 9, and is due 2010 August 30, 2010 at 12:00 PM (Pacific Daylight Time)

Get ready to attend the CT Tutorial to be given by Intel’s Dr. Michael Klemm, at the Nineteenth International Conference on Parallel Architectures and Compilation Techniques (PACT) September 11-15, 2010 in Vienna Austria. Registration for the conference is well underway and you can even register the week of the conference.

Superscalar Programming 101 (Matrix)
For this 5-part article, ISN Black Belt Jim Dempsey takes a small, well-known algorithm, shows a common approach to parallelizing that algorithm, follows with a better one and lastly, produces a fully cache-sensitized approach. Readers of this article will learn a methodology for interpreting test run statistics and to improve their code using those interpretations.

The Intel Math Kernel Library 10.3 Beta has been Released
Intel® Advanced Vector Extensions (Intel AVX) optimization
Summary Statistics library - modern algorithms that enhance accuracy and performance of statistical computations.

Intel Developer Forum Returns to San Francisco, Sept. 13-15

If you have questions you'd like to see up discuss, ideas for show topics or just want to send fan mail....
Send Email to parallelprogrammingtalk@intel.com

On Today's Show:

Clay will be discussing the recently completed Thread Challenge problem.

Connected Components in a Graph

Write a threaded program to compute the number of connected components and the maximum and minimum number of nodes from among the connected subgraphs within an input graph.

Prime Array Search

Write a threaded program that finds an example of a prime array that has the maximum number of primes hidden within it for a given array size.

Coming up next on Parallel Programming Talk...
Prof. Alexandra Fedorova - Managing Contention for the Shared Resources on Multicore Processors
Date/Time: 8/10/2010 at 8:00 AM Pacific - Watch Live on ISN TV

Set your alarm to watch Parallel Programming Talk Tuesday at 8:00AM PT on Intel Software Network TV.
LinuxCon 2010 Wrap Up and Highlights

Posted: August 20th, 2010, 10:32am MDT by Lisa Hoover
LinuxCon North America 2010 wrapped up last week. If you weren't able to attend, here are some highlights of what you missed:
- Stormy Peters, executive director of the GNOME Foundation, used her keynote to implore developers to use free software when creating Web services. Peters says the lack of Web services based on free software is troubling -- developers should be "embarrassed" by it and push for change. She also encouraged people who use Web services to be mindful of privacy and data-sharing concerns. "In addition to encouraging developers to build new free software-based Web services, Peters said free desktop software needs to be better integrated with Web services. One challenge is that more developers are building for the Web and could use tools to build desktop apps that work with the Web," writes CIO's Bob Brown.
- Red Hat executive and Linux kernel contributor Matthew Garret led a discussion called Android/Linux: Lessons Learned. He defended Google's decision to partially fork Android's code and leave it out of the kernel for the time being. "He said one major difficulty is that Google’s wave lock code is unique to Android and not a baseline technology that would be used by other mobile platforms. The 'partial forking' is disappointing but much better than not having any open source mobile platform to compete against Apple’s iPhone," writes ZDNet's Paula Rooney.
- The Linux Foundation announced the formation of the Open Compliance Program, an initiative designed to help companies comply with open source licensing requirements. With support from big name companies in the software industry like Adobe, IBM, Sony, and Intel, The Linux Foundation put together tools and training materials businesses can use to understand the nuances of open source licenses and make sure they stay within established guidelines for the licenses they choose.
- MeeGo Community Manager Dawn Foster gave an informative presentation about the status of the MeeGo project and its surrounding community. She reviewed the project's progress, including the recent releases of the fully functional netbook code and the limited functionality handset code for developers. Foster says plans for MeeGo's immediate future include taking steps to further unify the community and build a strong ecosystem around the project. For an in-depth look at Foster's presentation, check out the slides [PDF] posted on MeeGo's Web site.
If you're outside of North America, make plans to attend LinuxCon Brazil at the end of this month or LinuxCon Japan in September.
nulstein v2 plog- presenting through a blog

Posted: August 20th, 2010, 10:22am MDT by Jérôme Muffat-Méridol (Intel)
It was a great pleasure for me to finally present this work at GDC Europe 2010, and given the attendance was phenomenal, with a room too small to seat everybody, it makes sense to make this content available to more people. I was pondering that in Cologne, the last few days while people were coming back with questions, and the usual feeling was hitting me: there is so much more I wanted to say, and all these questions lead to such interesting discussions... The idea of presenting it again via this blog came naturally, it makes sense. A lot of sense:

Every other day or so, I could comment one slide in the talk, tell the part of the story that goes with it, but also digress as much as I want, throw in some ideas for the future. This should make me free from the length constraint of a talk, and of the linearity of a full fledged article.

But even better: you get to ask questions, interact with me and other readers through the comments. Please, if you have a question, get it in there, don't be shy: someone else probably also is (or will be) having the same question. Also, take advantage of the fact that this doesn't have to be linear: it's perfectly okay to come back to an older slide and comment or ask a question where it works best (so people finding his later on can take advantage of it too)

As things need names to really exist, let's call this a plog, half presentation, half blog (couldn't find a better name, best alternative I liked was frog, but it doesn't stand for anything).

Let's get started:

Hmmm, Hmmm (sorry, I hmmm-hmmm a lot)

Hi everybody, I'm Jérôme, I work as an application engineer at Intel and my work consists in working with games studio so we can make our respective technologies run great together. Over the next couple of months, instead of talking about how you can optimise your game engine for multicore, I will be talking about how I optimised my own (tiny) engine. It relies on two important technologies, and that's what we'll be mainly focusing on:
- stealing task scheduler: this provides the load balancing and serves as a spine for this project. It can be Intel Threading Building Blocks or the tiny scheduler from previous version.
- DirectX 11 deferred contexts: this exciting new feature lets us schedule draw calls from several threads at once, and will let us run 100% in parallel
next slide: now is multicore
Spoiler (slides+source code): here
International software workshop in Beijing

Posted: August 19th, 2010, 6:32pm MDT by Michael Wrinn (Intel)

I had the privilege to participate in a recent workshop at Peking University, a summer school on "global distributed software development", sponsored by an interesting organization called CPATHi18n, combination of Chinese and American universities, and the USA's National Science Foundation. Students (and these really were students -- more on that in a moment) came from China (of course -- about a third of the total), Korea, Japan, Canada and USA; instructors included both professors and industry types such as me (I met some from Microsoft Labs and IBM).

The "distributed" in the workshop title refers to the "distributed development", as in multi-location teams, not "distributed software", as in, say, grid applications. Nevertheless, the organizers considered parallel software development (as in "parallel software") to be so important they invited me to deliver four afternoon sessions focusing on the topic, so I flew to Beijing with a laptop full of powerpoint erudition on threading building blocks (generics, concurrent containers, scalable memory allocators) and their goodness in realizing classical algorithms -- old favorites like convolution, prefix scan, and quicksort. This somewhat stodgy preparation survived, like all battle plans, about one minute into the actual engagement. My normal workshop audience is professors, or sometimes working professionals, but here before me were actual university students, mostly the undergraduate variety. Not since my own grad school days had I been before such an audience, which had faded in memory to faint rumor. Ok, time for a new plan.

Luckily, the connection from campus (in Beijing) to Intel's Manycore Testing Lab (several 32-core systems in Dupont, Washington) was good, so we proceeded with coding exercises, starting with a parallel "hello, world" and moving up from there. As the week progressed, we also commandeered local systems to install and build parallel versions of "Destroy the Castle", and Intel game demo. The emphasis on coding turned out to be key, and it didn't hurt to have a game demo to break up the calculations of pi. Key learning for me (a "duh", in retrospect): keep students busy, with solvable puzzles. Hmm, maybe this approach can work for audiences of professors, too?
Parallel Architecture: From Adhocracy To Bureaucracy

Posted: August 19th, 2010, 5:11pm MDT by Asaf Shelly

Enclosure: [download]

These past few weeks I have been busy to the extreme. Some good events and some are less happy events. The most important of which is having our first baby boy. You can really test your time management skills when you have no time... A wise man once told me that there is always time: 24 hours per day. Having enough time depends of what you plan to do with it. People can't work 24 hours a day. There is something else other than time, things like concentration, focus, commitment... These depend on how interesting is your job and what else would you like to do. If you really try you might be able to put that aside and still invest enough efforts in your work. There is another thing which is more interesting for this discussion: Interruptions.

We called our baby boy Gad. Gad is one of the sons of Jacob in the bible (See wikipedia), he was number 7 in the list of 12. In Hebrew the meaning of the name Gad is luck and when adding the value of the Hebrew letters we get 7 (Gimatria). We are fortunate to have him. He is a good boy at the age of 3 and a half weeks. (Here he is at half that age: GadShelly). We didn't name him Gad because of good luck. Everyone around us are giving special and unique names to their kids, we figured it would be best to give him the simplest name we can find and let him cast his own character into this name.

Good boy or not, he is always seeking attention. A month ago my cellular phone was interrupting me when I was trying to put all my focus into something. If right now while I am writing these lines I had a phone call, I would probably not even get up to see who this is. I'll get back to them. Everyone who knows me already know to call me from a familiar number so I can get back to them. Before I sat down to write these lines I made myself a cup of tea. It is cold by now because I found myself going over emails and then writing this post. I have been wanting to get up to do something about this cup of tea, and it is still on my to do list. If I get up for something else hopefully I will remember to take the cup with me. I did however get up immediately when Gad was making a few noises. Love and care had nothing to do with it. There is something else there.

Babies are very demanding but this is not because they would interrupt more times or more rapidly. There are days when my phone would ring too often for me to do any work if I answered it. People came back from vacation, end of year and everyone need to clean things up etc. My cell phone plays a music I like. Calls from family members can have different a music. This is just like the CPU having Interrupts with several different priorities. This priority is according to the source of the event. If I want to know the urgency of the event I would have to pick up the phone and ask, or engage in a higher level protocol, just like a PCI Interrupt can be a mouse click or an out-of-battery event. If you call me two consecutive times I figure this has to be important so I will probably pick it up. If it wasn't then the next time you call me two consecutive times I will ignore...

Babies have a very low tolerance level. A baby can sleep for an hour and then wake up, look around and say "aa", "ooa", "we-a". This means something like "I am awake", "Food", "Food". If you do not respond then immediately they would start crying which means "Help me!",  "Help me!". If you do not respond to this then ten seconds after this the crying escalates to  "Emergency!",  "Emergency!". If you responded in time then the crying stops, as long as things are going in the general direction. When the baby figures out "Hey, this guy is just picking me up, where is the food?" we go back to escalation.

Right after child birth, we were at the hospital for two more days, and Gad was with us the whole time. They let you keep the baby with you if you want. I was with my wife so we took shifts taking care of him. For anyone who would prefer to get some sleep, the hospital has nurses in a nursery with which you can leave the baby and come back for feeding whenever you want. We were in that room for our baby's physical tests. A long and wide room full of tiny little babies. Statistically you would have 2 to 6 babies crying at any given time. Taking care of them are 3 to 5 nurses. Some of them do physical tests to other babies so they are 'out of resources' to handle every baby's  "Emergency!" call. It seems that most times babies would call  "Emergency!"  "Emergency!" and a minute later would forget about it and go back to sleep, or maybe they just get tired and reserve their energy for something else.

Some mothers ask the nurses to call them when the baby is crying, so if a baby is crying for long enough and there is a free nurse the mother would get a call. This makes the nurse teams into a dispatcher. Actually they are a collection of dispatchers with different tasks and responsibilities. If the mother didn't come to breastfeed for a long time, the nurses would feed the baby using a bottle. In this system every one of the clients define their event as hi- priority and the server decides who is really hi- priority by other parameters such as persistence, and understanding client's internals.

Imagine a web server which is now out of resources, flooded with requests. Some requests have to be ignored. Simple requests such as "give me your home page" can be answered because they are cheap to handle. A request for "Get all my friends list" requires some database action and the database is too busy. The request is ignored and the client will have a "refresh my list" button enabled so the user can ask again later. When a client is saving a document, this request will not give up so easily and the connection will remain open for up to 120 seconds. The web server will see a persistent connection and will figure that this has to be important if the client is willing to waste time for the action to complete. This describes a system which by design states that if an event is really important then the client would invest resources and efforts on making sure it is served. Do you know of such a system?

This sounds like a good plan for a system. Clients are eventually operated by people. If you have an HPC Cluster and the user can set the priority of his own tasks... well... In modern Hebrew there is a saying which loosely translates to The cook does not testify for his bakery. Maybe some student has a hot date and wants his tasks to finish first and that would slow down other tasks which are more important in the bigger picture. Priorities are dependant on the source of the request, but persistence and the amount of effort you are willing to invest in a request is also not a really good factor. It is possible that a young kid playing an online computer game be more persistent than a CEO of a big company trying to access his online bank account.

There are many systems who deal with a variety of requests from different people. Most of these systems are run by people and they make the final decision but most times there are clear-cut rules to what should and should not happen and how to handle a given request. Sometimes the system would initiate a follow-up interaction with a client in an attempt to understand the urgency and necessity of the request.  Such a system is called a "Bureaucracy".

A Bureaucracy is both good and bad. A national organization without bureaucratic rules will end up being corrupted. On the other hand a bureaucratic organization can sometimes be detached because the person making the request does not fit the profile of high priority client, which is a result of an imperfect rule base. Sometimes it is good that the system is indifferent to clients because an online game is not as important as police communications but as an individual you cannot see the big picture. If my HPC cluster could ask the student for the reason of urgency of his task and there would be something like "Personal" -> "Romance" -> "First Date", then my HPC cluster would know that it is not as important as "Personal" -> "Romance" -> "Wife's Birthday". Maybe this is too detailed but you get the point.

Today our software operates huge systems that justify Bureaucracy but their design is more similar to an Adhocracy.
Multitasking and iOs 4.0 - What it is and what it is not

Posted: August 18th, 2010, 5:13pm MDT by Code-Monkeys

For a while there it seemed Android phones really had the iPhone beat with a certain feature known as Multi-tasking. It was all over the news and yadda yadda yada. Then Apple announced an upgrade that now includes – wait for it – multitasking. But it may not be what you think it is. We want to take a moment here to answer a few FAQs about the multi-tasking mystique and to speak another obvious question – what’s this got to do with AppUp.

First, lets talk about the concepts here. When an operating system can multitask this is its ability to run more than one program at the same time. (Not to be confused with threads which are different) This gives each running program access to important system resources simultaneously and the user gets the ability to do several things at once. For example an MP3 player bopping along while your email client checks POP3 while you’re editing a text document. When it comes to our desktop systems – we’ve come to expect this kind of behavior as minimal requirements. But prior to iOS4 the iPhone didn’t allow any third party processes (read: your app) to continue running after it lost focus. In fact, the iPhone “single-thread” experience has become a marketing point in many places and people started rediscovering the mental clarity of doing one thing at a time. It should be noted however that Apple always kept certain classes for their own use and apps like iCal were treated as a special case, often behaving in a multi-tasking kind of way. It just was something mere mortals were forbidden to do.

read more
GDCE2010: How will next release of Intel GPA look like?

Posted: August 18th, 2010, 8:13am MDT by Michael J Huelskoetter

During Game Developers Conference Europe 2010 we had the opportunity to talk to Aaron Davies from Intel who is in charge of their tool suite Intel Graphics Performance Analyzers which you can use for detecting bottlenecks in your game code. If you wanna learn more about Intel GPA you can watch the related video post which we created right here at GDCE 2010.

What we've learnt from Aaron are four things:

1. The next Intel GPA release will be announced during GDC 2011 which will take place in San Francisco around March timeframe.

2. The Intel GPA update will correspont to the announcement of Sandy Bridge, Intel's next micro-architecture which will follow the current Nehalem architecture. Therefore tools like Intel GPA will align with new technologies like Sandy Bridge and thus offer new features which will perform best on new Intel platforms.

3. The new feature "Platform View" which is still in beta will become a "real" feature and the third component of next Intel GPA release.

4. Finally - as Intel is keen on supporting software developers all over the world - Intel GPA will be available for free as it's helpful, efficient and will thus help game developers creating flawless and performant gaming titles. And Intel GPA is cross-platform, which makes it even easier to get the right tool for your developing environment.

So, and if you wanna watch our video interview, just go and push the button!
GDCE2010: Finding bottlenecks in games with Intel GPA

Posted: August 18th, 2010, 8:12am MDT by Michael J Huelskoetter

During day one at Game Developers Conference Europe 2010 I attended a really interesting tech session which was held by Steve Hughes from Intel. I've blogged about it already but as this was a quite short post about Steve's session I will add some more details.

First thing you should know about Intel GPA are the new features which are part of this tool suite since release #3. Highlights are the new Platform View, DX10.1 support, better performance on Intel HD graphics and many more.

Second: you should be aware of that Intel GPA lets you drill down very quickly into your game code in order to find bottlenecks which slow down your game.

Third: thanks to the client-server-model of Intel GPA you have a small impact on your testing machine whereas Intel GPA runs on one PC and the targeted game on a second machine which are connected via ethernet.

Fourth: Intel GPA consists of three tools: System Analyzer, Frame Analyzer and Platform View which is quite new since release 3.0.

Video tip: If you'd rather listen to Steve's words than reading all theses slides please refer to our video interview where Steve answered our three short questions regarding Intel GPA.
GDCE2010: Parallelize your Games with Intel Threading Building Blocks

Posted: August 18th, 2010, 5:35am MDT by Michael J Huelskoetter

Here at Game Developers Conference Europe 2010 Dr. Mario Deilmann from Intel talked about "Parallelizing Games with Intel Threading Building Blocks". As I followed his tech talk and took some pictures of his presentation it's time to summarize his speech and what you as a developer can learn from Mario's session.

1. Functional decomposition of games is limited as it doesn't scale properly on n-core systems. That's why you should decide to follow the tasks model as it scales on dual-, quadcore and n-core machines best.

2. If you wanna extend your C++ based games to parallelism you should consider using Intel TBB as it does thread management, scales on available hardware threads properly, support nested parallelism and many things more.

3. Clicking through our Flickr gallery of Mario's presentation help you to understand Intel TBB and its functionalities better. So learn about the fundamental principle of Intel TBB and some details about the TBB task scheduler (which supports task stealing).

4. If you want to know the differences between the traditional parallelizing of games and the Intel TBB approach then Mario's presentation is suitable, too.

5. More things to learn by Mario: possible effects of task-to-thread affinity, that you should use Intel TBB's parallel memory allocators, that using the Intel TBB's parallel_for() construct is a 2-step process, that there are more Intel TBB parallel loop patterns which can be used and that you can use Intel TBB's low-level API to implement useful threaading patterns.

And if you don't believe that well-known game developer companies use Intel TBB already you can be convinced quickly.

Video tip: If you belong to those people who'd rather watch TV than reading an article you should give our video interview a try...
Extracting X509 certificate fields for use in the workflow.

Posted: August 18th, 2010, 5:14am MDT by Pete Logan (Intel)
Following on from my last blog post I want to go deeper into some of the flexibility Intel® SOA Expressway gives you when authenticating requests with some WS Security or other digital certificate sent with the message. It's all good and convenient when you know that you need to extract the cert subject and pass that to LDAP for authentication but what about the cases where you need to examine a token within the workflow which would both be simpler to do than call out to a policy decision point like LDAP or Oracle* Access Manager and much, much quicker?

Method 1:
Choose a custom GetSOAPHeader workflow action that extracts out the Security node with the wsse namespace for WS Security. this is followed by an extension function in an f(x) action:

soae-xf:get-certificate-field$GetSOAPHeader//*[local-name() = 'BinarySecurityToken'], 'subject-name')

which (for our built in demo certificate) then gives:

CN=SarvegaDemoCert,OU=Support,O=Sarvega, L=Oakbrook Terrace,ST=Illinois,C=US

What else can you pop out of the certs then? Well the whole set of stored data which includes:
- subject-name
- ski
- generated-ski
- generated-short-ski
- sha1-fingerprint
- md5-fingerprint
- issuer
- serial-number
As usual with Intel® Services Designer there's a couple of ways to do things depending on your preferences so here comes...

Method 2:

Use the AAA workflow action to extract the certificate subject name. It’s a three step process:
1. 1. AAA workflow action and policy to get the full cert from the WS Sec header.
  2. GetSecurityMetadata workflow action retrieves the text of the Certificate.
  3. And the extension function is changed to look like:
soae-xf:get-certificate-field($GetSecurityMetadata, 'subject-name')

Pros and Cons of each method:

The AAA plus policy and extra BPEL action step will be slower as there is an extra workflow action step and the AAA policy to read in but it more accurately extracts the X509 certificate from the binary security token node of the WS Security header. The first method may be faster but you need to be aware that you cannot just pass the whole SOAP header to the get-certificate-field and expect it to find the certificate. Instead you need to narrow down what gets passed to it and weed out any other SOAP headers like WS Addressing and WS Security Timestamps by using XPath.

*Other names and brands may be claimed as the property of others.
Get Your Invite to Intel AppUp Elements 2010

Posted: August 17th, 2010, 7:10pm MDT by Bob Duffy (Intel)

Because its the party to be at!

Opportunity Knocks Register by September 1st to get your registration fee waived ($795 value)! Following immediately after IDF is the conference that goes deep, wide, serious and crazy about mobile app development for the Intel AppUp Center. So join us for an extraordinary event both exclusive and stimulating: collaboration with fellow innovators, software developers, global entrepreneurs, industry experts, thought leaders, and more. Learn more about opportunities for application monetization as new device categories and platforms emerge. Share your skills and your apps in dynamic conversations with peers and influencers. Explore new possibilities for creativity and revenue across multiple platforms, runtimes, devices, storefronts, and distribution options. Register now to secure your seat at this invitation only event! read more
Get Your Invite to Intel AppUp Elements 2010

Posted: August 17th, 2010, 7:10pm MDT by Bob Duffy (Intel)

Because its the party to be at!

Opportunity Knocks Register by September 1st to get your registration fee waived ($795 value)! Following immediately after IDF is the conference that goes deep, wide, serious and crazy about mobile app development for the Intel AppUp Center. So join us for an extraordinary event both exclusive and stimulating: collaboration with fellow innovators, software developers, global entrepreneurs, industry experts, thought leaders, and more. Learn more about opportunities for application monetization as new device categories and platforms emerge. Share your skills and your apps in dynamic conversations with peers and influencers. Explore new possibilities for creativity and revenue across multiple platforms, runtimes, devices, storefronts, and distribution options. Register now to secure your seat at this invitation only event! read more
Candid Letter To Intel, Asks Us to Wake-Up about AppUp

Posted: August 17th, 2010, 4:50pm MDT by Bob Duffy (Intel)

blockquote { margin: 1em 3em; border-left: 2px solid #999; font-family: verdana; font-style: italic; padding-left: 1em; }
Chris Skaggs of Soma Games, and an active member of the Atom Developer Program posted an interesting blog this week on the Soma Games site titled: An Open Letter to Intel on The AppUp Center. For full disclosure Chris also works for Code Monkeys, who Intel has contracted with for providing software development services to port apps to AppUp. To say his letter is candid is a bit of an understatement, and Chris admits his reservation about writing the post by saying:
read more
Candid Letter To Intel, Asks Us to Wake-Up about AppUp

Posted: August 17th, 2010, 4:50pm MDT by Bob Duffy (Intel)

blockquote { margin: 1em 3em; border-left: 2px solid #999; font-family: verdana; font-style: italic; padding-left: 1em; }
Chris Skaggs of Soma Games, and an active member of the Atom Developer Program posted an interesting blog this week on the Soma Games site titled: An Open Letter to Intel on The AppUp Center. For full disclosure Chris also works for Code Monkeys, who Intel has contracted with for providing software development services to port apps to AppUp. To say his letter is candid is a bit of an understatement, and Chris admits his reservation about writing the post by saying:
read more
Which comes first: parallel languages or parallel programming patterns?

Posted: August 17th, 2010, 3:43pm MDT by Clay Breshears (Intel)
On the shuttle to the recent UPCRC (Universal Parallel Computation Research Center) Annual Summit meeting on the Microsoft campus in Redmond, WA, I was listening in on a discussion about parallel programming patterns. Being a parallel programmer, I was interested in what people (and these were some of the experts in the field) had to say about parallel programming patterns, how they are evolving and how they will impact future parallel coders. The discussion turned to whether patterns would affect programming languages directly or remain something that would be constructed from statements of the language. I think I'm in the former camp. Here's why.

For those of us that were programming when Elvis was still alive, think back to writing with assembly language. For the most part, there were instructions for Load, Store, Add, Compare, Jump, plus some variations on these and other miscellaneous instructions. To implement a counting/indexing loop you would use something like the following:
```
      Initialize counter
LOOP: test end condition, goto EXIT if done
      Loop Body
      increment counter
      goto LOOP
EXIT: next statement
```
This is a programming pattern. (Surprised?) With the proper conditional testing and jumping (goto) instructions within the programming language, this pattern can be implemented in any imperative language.

Since this pattern proved to be so useful and pervasive in the computations being written, programming language designers added syntax to "automate" the steps above. For example, the for-loop in C.
```
for (i = 0; i < N; ++i) {
   Loop Body
}
```
Once we had threads and the supporting libraries to create and manage threads, parallel coding in shared memory was feasible, but at a pretty crude level since the programmer had to be sure the code handled everything explicitly. For example, dividing the loop iterations among threads can be done with each thread executing code that looks something like this:
```
   start = (N/num_threads) * (myid)
   end = (N/num_threads) * (myid + 1)
   if (myid == LAST) end = N
   for (i = start; i < end; ++i) {
      Loop Body
   }
```
Parallel programming patterns will be abstractions that can be "crudely" implemented in current languages and parallel libraries, like the pseudocode above. New languages (or language extensions) will make programming parallel patterns easier and less error prone. From the example above, OpenMP has the syntax to do this, but it only takes a single line added to the serial code...
```
#pragma omp for
   for (i = 0; i < N; ++i) {
      Loop Body
   }
```
From the evidence above, I think future parallel programming languages or language extensions supporting parallelism will be influenced by the parallel programming patterns we define and use today. And nothing will remain static. Ralph Johnson (Design Patterns), during his presentation, remarked that some of the original patterns saw early use, but this use has slacked off. Two reasons he noted for this was that some of the patterns couldn't easily be implemented in Java and modern OO languages had better ways to accomplish the same tasks--most likely these new languages found inspiration from the patterns and their usage.

For an answer to the quesiton posed in the title it boils down (no pun intended) to the old chicken and egg paradox. There were algorithms (patterns) to do computations before there were computers; prior to that, those algorithms were modifications of previous algorithms influenced by the tools available. Looking forward, though, we're still in the relative stages of infancy for programming, let alone parallel programming. Clearly, the next generation of parallel programming languages or libraries or extensions bolted onto serial languages will be influenced by the patterns we use now for specifying parallel computations.
Which comes first: parallel languages or parallel programming patterns?

Posted: August 17th, 2010, 3:43pm MDT by Clay Breshears (Intel)
On the shuttle to the recent UPCRC (Universal Parallel Computation Research Center) Annual Summit meeting on the Microsoft campus in Redmond, WA, I was listening in on a discussion about parallel programming patterns. Being a parallel programmer, I was interested in what people (and these were some of the experts in the field) had to say about parallel programming patterns, how they are evolving and how they will impact future parallel coders. The discussion turned to whether patterns would affect programming languages directly or remain something that would be constructed from statements of the language. I think I'm in the former camp. Here's why.

For those of us that were programming when Elvis was still alive, think back to writing with assembly language. For the most part, there were instructions for Load, Store, Add, Compare, Jump, plus some variations on these and other miscellaneous instructions. To implement a counting/indexing loop you would use something like the following:
```
      Initialize counter
LOOP: test end condition, goto EXIT if done
      Loop Body
      increment counter
      goto LOOP
EXIT: next statement
```
This is a programming pattern. (Surprised?) With the proper conditional testing and jumping (goto) instructions within the programming language, this pattern can be implemented in any imperative language.

Since this pattern proved to be so useful and pervasive in the computations being written, programming language designers added syntax to "automate" the steps above. For example, the for-loop in C.
```
for (i = 0; i < N; ++i) {
   Loop Body
}
```
Once we had threads and the supporting libraries to create and manage threads, parallel coding in shared memory was feasible, but at a pretty crude level since the programmer had to be sure the code handled everything explicitly. For example, dividing the loop iterations among threads can be done with each thread executing code that looks something like this:
```
   start = (N/num_threads) * (myid)
   end = (N/num_threads) * (myid + 1)
   if (myid == LAST) end = N
   for (i = start; i < end; ++i) {
      Loop Body
   }
```
Parallel programming patterns will be abstractions that can be "crudely" implemented in current languages and parallel libraries, like the pseudocode above. New languages (or language extensions) will make programming parallel patterns easier and less error prone. From the example above, OpenMP has the syntax to do this, but it only takes a single line added to the serial code...
```
#pragma omp for
   for (i = 0; i < N; ++i) {
      Loop Body
   }
```
From the evidence above, I think future parallel programming languages or language extensions supporting parallelism will be influenced by the parallel programming patterns we define and use today. And nothing will remain static. Ralph Johnson (Design Patterns), during his presentation, remarked that some of the original patterns saw early use, but this use has slacked off. Two reasons he noted for this was that some of the patterns couldn't easily be implemented in Java and modern OO languages had better ways to accomplish the same tasks--most likely these new languages found inspiration from the patterns and their usage.

For an answer to the quesiton posed in the title it boils down (no pun intended) to the old chicken and egg paradox. There were algorithms (patterns) to do computations before there were computers; prior to that, those algorithms were modifications of previous algorithms influenced by the tools available. Looking forward, though, we're still in the relative stages of infancy for programming, let alone parallel programming. Clearly, the next generation of parallel programming languages or libraries or extensions bolted onto serial languages will be influenced by the patterns we use now for specifying parallel computations.
GDCE2010: Tech session summary: "Multi-thread games with DirectX 11"

Posted: August 17th, 2010, 6:21am MDT by Michael J Huelskoetter
Day two at Game Developers Conference Europe 2010 started for me at 9:00 am sharp, as Jerome Muffat-Meridol from Intel held his presentation "UFO invasion: DX11 and Multicore to the Rescue". The good news: the room was really packed with developers although it was quite early and the barbecue party yesterday night was really good what I heard so far!

For all of you guys who couldn't attend Jerome's tech session I shot some pictures and put them on Flickr. Jerome had some interesting thing to show and to tell:
- The multicore era has started already, but parallelism in apps and games for many developers is still a future topic
- Divide and surrender when thinking of the good old days of executing game code
- Different stages of game execution is highly parallel, but the execution itself is still real sequential!
- Compared to typical task schedulers an improved task scheduler which is being used within the nulstein demo are based on task stealing which helps use available thread resources as best as possible
- the "trick" of the nulstein demo and its highly performing multi-threading code: all "things" in the game are entities which can be manipulated and executed in parallel
- Updates on entities are mostly dependent!
- But we learnt a lot about rendering processes within the nulstein demo as well! And about multi-threaded rendering with DirectX 11.
- And the funniest thing about nulstein demo: multi-threading with DirectX 11 has no impact on runtimes at all! But: although DirectX 11 doesn't scale (due to missing drivers) it has an impact as frames will be rendered faster as the whole system works orthogonally!
So, and if you are really keen on hearing more about Jerome's presentation we have good news for you: we have interviewed him after his presentation and will present the result as a video clip soon. So, stay tuned...
GDCE2010: Day one summary: Intel GPA, netbook games and Havok Physics

Posted: August 17th, 2010, 3:17am MDT by Michael J Huelskoetter
The first day here at Game Developers Conference Europe 2010 is almost done and so it's time for a first summary what happened so far.

The first Intel tech session was held by Steve Hughes who talked about Intel Graphics Performance Analyzers. This tool suite helps game developers to profile and debug their products in order to find bottlenecks and other annoying things. Steve presented the new features of Intel GPA 3.0, showed how to use the three different tools (System Analyzer, Frame Analyzer, Platform View) und how these tools help game developers to instantly view modifications on single frames. Moreover we learnt, that the SDK and a capture tool are included, that Intel GPA runs as a client-server tool to minimize the impact on the tested platform and you can drill down quickly into your game.

Tech session number two was held by Intel's software engineer Leigh Davies and hold the title "Building Games for Netbooks". Leigh's presentation was fully-packed with lots of interesting thing like:
- ad-hoc Gaming for Netbooks is quite easy with Intel Laptop TDK
- how to invoke the Intel Laptop TDK
- how you maximize the Intel Atom processor performance with Threading and SSE
- which vectorization options you can use on Intel Atom processor
- how you optimize your game for Intel Atom processor machines with appropriate compiler switches
- and much more
Moreover we had the chance to talk to the Havok guys who share the showcase booth with Intel. We set-up our video camera and created three video clips which show how Havok physics work in general, in terms of desctruction and cloth. So, just click the related link and watch the video. Have fun!
Discovering JQuery for web based authoring

Posted: August 15th, 2010, 10:00pm MDT by Ylian Saint-hilaire (Intel)

Ok, so maybe I am the last web developer on earth to discover JQuery. I have to say, I am impressed with this little library. A few months ago, James, a rotation engineer at Intel worked for my group at Intel and introduced me to JQuery for doing AJAX calls. I used it a lot last month when building the Javascript VT100 terminal. This last week, I make use of JQuery again in a completely different way. I used it to create HTML visual effects and it works really well.

I started by typing "JQuery effects tutorial" in Google and found this tutorial. The samples are easy to follow. I did have to get the hang of this stuff, it's not immediately evident how it all works, but I started coding and 30 minutes later I have an animated panel for my own web site.

We are working on the configuration page for associating Twitter accounts to MeshCentral, and since we expect to add support for many social sites, I wanted a configuration page that could fold and show only the configuration sections that the user cared about. With JQuery, I want able to create a set panels the user could show and hide. Best of all, the transition is animated. Below is the screen shot of the page.

By the way, we got the Twitter feature almost ready. Should not be long now before anyone can use it.

Ylian
meshcentral.homeip.net
Get Your non C/C++ apps in AppUp with Free Component

Posted: August 15th, 2010, 6:59pm MDT by Bob Duffy (Intel)

Free AppAble Component from BaKno Games for Limited Time

There are many value propositions for the Atom Developer Program. On is a more open and broadening means to develop apps to monetize and distribute thru AppUp. The other is that our community is enabled to provide solutions as market opportunities for app development through AppUp.

Both of these are true with the AppAble 2.0 solution from baKno Games. AppAble is a components solution that allows many non C/C++ Windows apps to be submitted to the AppUp store. Although our SDK for Windows only supports C/C++ apps, AppAble allows for apps developed in in UnityPro, Run Revolutions, C# (.NET), Python, Ruby, Java, & Flash to use the AppUp sevice by providing a C/C++ layer for the needed AppUp calls.
read more
Nothing but "Net" - book - On vacation with a Netbook and AppUp

Posted: August 14th, 2010, 1:16pm MDT by Russ Beutler

I am going on vacation next week - yes it happens at Intel believe it or not. During this time I will be leaving my work laptop home and relying on a trusty new netbook and applications that are available today on theIntel AppUp center.
read more
Neuron 3DS Max 2011 tool ribbon

Posted: August 14th, 2010, 11:30am MDT by Randy of Neuron

I have been a user of 3DS Max since the DOS version when it was called 3D Studio. Now that we have purchased the 2011 version I would like to add my two cents to the 3D modeling world regarding 3DS Max 2011.

The more I use the new version the happier I am, however there are some things I would like to see added. A tool ribbon covering the old version basics is one of them. I know that everyone likes there own UI configurations, but it would have been nice for Autodesk to supply several ribbon configurations for free. Especially those that covered the most common and basic tools. The 2011 version wants a user to use the create menu on the right side which is not the most efficient. If you think about it, an artist is a right brained creator that thinks in pictures, so I am used to just looking for the icon image of a sphere and clicking it to make a sphere. Nothing breaks my creative mood like having to read through a list of objects to create and find the one that I want to use. It is slow, cumbersome, and a buzz kill.

The great news is that 2011 version of 3DS is so configurable that you can get this look and feel back which has greatly sped up our productivity. So I share the interface here for you to download :)

Here is an overview of the tool ribbon that I have created that adds literally hundreds of tool shortcuts to all the basics that 3DS used to provide shortcuts to. I am sure as I use 2011 more and more I will modify this tool bar configuration and provide it here.

I added two ribbon tabs, Create and Modeling. Under the Create tab I have created the following tool panels.

Create - Shapes Tools

Standard Shape creation primitives, or at least them most commonly used ones. I don't even use some of these but rarely.

Create - Objects Tools

Standard object primitives, as well as a few not so conventional or used.

Create - Architect

These are the architectural tools that come in quite helpful when building structures. No longer do you have to create exteriors or interiors from compete scratch.

Create - Lights and Cameras Tools

Traditional light and camera tools, even the new photo realistic tools. There are some other camera tools that might be added to this later such as the exposure tool and so on. I will have to see how often we use them.

Create - Helpers Tools

The traditional helper tools that come in quite helpful (snicker)

Create - Particle Systems Tools

As the title implies, tools for adding particle systems to your scene.

Create - Dynamics and Systems

Probably more will be added to this section, but quite a bit will be in the new reactor tools so look below.

Create - Reactor Tools

Short cuts to all the new reactor physics tools. There is so many cool things in this panel from Rag-Doll physics, Wind, Water, and even stuff like fractures. Pretty cool.

Modeling - Modeling Tools

As the title says, the most typical modeling tools. Keep in mind these are not modifiers for existing objects, but rather creation tools. I broke them up so the modifiers are separate.

Modeling - Compound Tools

The compound tools such as booleans and stuff like that. Happy happy joy joy!

Modeling - Modifiers Tools

Probably the most used tools of all, the modifier tools. I thought about moving this to the front of the modeling tools, but I will have to see. I kind of like it centrally located.

Modeling - Space Warps Tools

The last, but probably not forever, the Space Warps tools. Awesomeness.

So you are welcome to use the link above, download the ribbon, right click on your own 2011 ribbon. Then go to customize and the dialog will open. In the bottom right you can click load and install this puppy. If you use it and find something more helpful please drop us a note. This ribbon will probably change over time. Cheers.

You can read more and follow me and Neuron Games, Inc. here:
Nothing but "Net" - book - On vacation with my Netbook and AppUp

Posted: August 14th, 2010, 11:01am MDT by Russ Beutler

I am going on vacation next week - yes it happens at Intel believe it or not. During this time I will be leaving my work laptop home and relying on a trusty new netbook and applications that are available today on the Intel AppUp center.
Why Concurrency is Dead

Posted: August 13th, 2010, 7:47pm MDT by Matthew Wolf

OK... Now that I have you hooked, let me explain what I mean. I don't mean that the concept of concurrency is dead -- far from it. What I mean, instead, is that we should stop using the word as if it means some sort of distinctive programming model. It's all parallel, folks.

This is all prompted by a series of comments I've gotten over the summer from several different sources, complaining that when I was discussing parallelism in education that sometimes I was talking about concurrency instead. Not to be overly harsh on those who put forward those complaints, but they seemed to be stuck in a time loop where there were some very real differences between the tools and programming models that one would use depending on the type of problem. If fork/exec solves your issues, then your problem is likely concurrent. If it doesn't, or if you have to do something funky once you've used fork/exec like used SysV-style shared memory, then you're writing parallel code. However... those distinctions don't make as much sense today.

So what happened? Time. And some really good thinking on what it means to be parallel in the first place. And a complete retooling of the way operating systems and languages deal with shared state between processes and/or threads and/or tasks. And development of much more complete programming infrastructures for dealing with parallelism. With copy-on-write and read-copy-update techniques (already inside your favorite OS), template- and library-based inherent parallelism (like TBB or math libraries), novel models with implicit parallelism (like Map-Reduce), and language extensions for parallelism (like OpenMP), we're operating in a very different *software* world from where we were 25 years ago, let alone the hardware changes.

So let's lay this to rest. Concurrency is still a useful term in the same way that phlegmatic is -- useful descriptions, but not diagnostic states in and of themselves. Modern medicine has moved beyond worrying about bleeding out the ill humors... I believe that we in CS can move beyond concerns of separating our "parallel" from our "concurrent" as well.
Parallel Programming Talk #87- Brock Taylor, HPC Cluster Solutions Architect

Posted: August 13th, 2010, 4:55pm MDT by Aaron Tersteeg (Intel)

Enclosure: [download]

Welcome to Parallel Programming Talk #87. Today is July 27th and we'll be talking with HPC Cluster Solutions Architect Brock Taylor.

Download Link - High Quality MP4 Video File (Large):

Download Link - MP3 Audio File (Small):

First The News:

Our Threading Challenge Phase 2 problem 1 is due Monday, August 30, 2010
(Apprentice: Bonev Sequences. Master: Taxi Paths.)
Problem 2 Starts on August 30th and ends September 20th.

Get ready to attend the CT Tutorial to be given by Intel’s Dr. Michael Klemm, at the Nineteenth International Conference on Parallel Architectures and Compilation Techniques (PACT) September 11-15, 2010 in Vienna, Austria. Registration for the conference is well underway and you can even register the week of the conference.

Superscalar Programming 101 (Matrix) Part 1 through 3 have been published.
For this 5-part article, ISN Black Belt Jim Dempsey takes a small, well-known algorithm, shows a common approach to parallelizing that algorithm, follows with a better one and lastly, produces a fully cache-sensitized approach. Readers of this article will learn a methodology for interpreting test run statistics and to improve their code using those interpretations.

Intel Developer Forum Returns to San Francisco, Sept. 13-15

SC10 - The Super Computing Conference is being held November 13-19, 2010 in New Orleans.
If you have questions you'd like to see up discuss, ideas for show topics or just want to send fan mail....
Send Email to parallelprogrammingtalk@intel.com

On The Show Today:

Intel HPC Cluster Solutions Architect Brock Taylor

Watch Parallel Programming Talk Every Tuesday at 8:00AM PT on Intel Software Network TV.
Dynamic Endpoint Lookup from IBM* WebSphere Registry and Repository

Posted: August 13th, 2010, 2:56pm MDT by Edward Shortnacy (Intel)

This is the first in a series of blog postings regarding various aspects of SOA governance and thoughts around how to leverage various ecosystem components to found a governance methodology that is right for your organization. In this posting we will start with a technique that is part of runtime SOA governance, dynamic endpoint lookup using a service gateway, namely Intel® SOA Expressway. First we’ll review a little history of where we came from to put this into perspective.

A decade or so ago the industry developed a standard known as Universal, Description, Discovery and Integration or UDDI. The focus of this standard was to locate details about internet resources in a standards based way perhaps as a way to move forward from X.500/LDAP based security stores. While it received a good deal of traction in large enterprises for this aspect of SOA governance, connecting and querying a UDDI server isn’t without its own challenges due to version compatibility and perhaps even vendor implementation. The closing of UDDI as an ongoing standards development effort by OASIS has led major enterprise software vendors to focus new efforts on their own Repository solutions. Several of the Repository vendors have formed a new effort called SOA Repository Artifact Model & Protocol (S-RAMP) to standardize access to these repositories for development, runtime and monitoring.

Just as many vendors used LDAP as a basis to begin their own enterprise security solution most of the Repositories generally synchronize with UDDI and digest web service and other XML metadata in a similar fashion. In addition to this UDDI like functionality, however, there are often hooks to their offerings in other important aspects of SOA governance putting this type of solution at the intersection of the service lifecycle. IBM*’s WebSphere Registry and Repository (WSRR) is one such product that we will look at leveraging for dynamic endpoint lookup.
We’ll begin with another important aspect of SOA governance, design time. Intel’s SOA Expressway runtime is configured by packages developed in Intel SOA Expressway Services Designer which is an Eclipse based integrated design environment. A great deal of design time governance for writing code in an IDE such as Eclipse centers around a source code control system and in this respect, Services Designer is no different but that’s another topic for another blog posting. Since these source code management infrastructures tend to be somewhat departmental, we’ll look at UDDI and Repositories as a means for those developing enterprise standard web service definitions to share their code with the SOA developer audience at large.

When starting a new project of type ‘Service Proxy’ in Services Designer you have the ability to query a UDDI server or Repository:

In this case we’ll look for our WSDL in a UDDI query:

If you’d like to test this scenario on your own you don’t need to replicate your IBM WSRR with UDDI you can sign up for an evaluation of Intel SOA Expressway here and we’ll provide a simple WSDL you can use for calling a remote service on the internet. In this case we’ll retrieve the definition of a simple calculator service and use it in our Services Designer which has an Eclipse modeling perspective based on Business Process Execution Language or BPEL. The initial project workflow created from the WSDL will look like this:

This is a simple proxy service that will allow you to receive a call on the Intel SOA Expressway service gateway and to invoke a remote function which happens to be a web service, although it could be mediated to one of many protocols supported (see data sheet for list). Notice the bottom of the following screenshot where the remote URL that will call in the ‘Invoke’ step is an un-routable host IP of 255.255.255.255. This could be the IP address of development server perhaps but in this blog we’re focusing on SOA runtime governance so let’s look at how we can dynamically derive the endpoint of the calculator service for its production instantiation using IBM WSRR as the authoritative source.

To do this we will put in another ‘Invoke’ to call out to IBM WSRR for this information. The invoke steps have been renamed to WSRR_Lookup and Calculator respectively in the following screen shot:

In this IBM* WSRR invoke we will configure the parameters we need to be able to execute our dynamic endpoint lookup. Since IBM* WSRR requires HTTP Basic Authentication for connections of this type by default we will provide Base64 encoded user name and password in an HTTP header entry. Here is an online utility you can use in order to encode your user name and password in the format of username:password. Once you get the result you would add the string “Basic “ in front of the generated Base64 string. Next we will enter the Path to the RESTful XMLPropertyQuery provided by IBM WSRR. Finally we will enter the Query we want to execute to get the endpoint of the Calculator service we would like to call at runtime. A couple of items to note here are 1) We’ve selected a simple static query string here where we know the name of the SOAP Address we’re looking for. IBM WSRR provides a wealth of governance capabilities for managing how this discovery is exposed in the real world providing far more interesting lookups containing more SOA governance centric parameters and 2) Although we are providing the name of the SOAP Address object that we want the location for from WSRR in the Query string, this could be reflected from the WSDL and passed in to this lookup making it a re-usable template which again, is another matter we will cover in a future posting focusing on best practices for development of SOA.

Once we’ve done this we have one last step to leverage the endpoint we want to dynamically discover from IBM WSRR at runtime and that is to extract the value of the location variable returned using XPath. We do this by selecting our Calculator invoke in our Workflow and then the Routing configuration on the left side vertical tabs. In this case we will leverage ‘Specify dynamic address’ and provide an XPath snippet in order to get the endpoint we want.

What we see now on the default Details vertical tab for our Calculator invoke is that the endpoint Service URL now refers to this dynamic location queried and extracted from IBM* WSRR.

In order to prepare to deploy our test to the Intel SOA Expressway we need to export the project from Eclipse which essentially rolls up project artifacts into a gzipped TAR file. We can import this file to the Intel SOA Expressway via several mechanisms, some of which will serve our future postings on SOA governance for the development lifecycle. For now we will look at the Web Interface for Intel SOA Expressway as there is one other item we need to accomplish to prepare for connecting to IBM* WSRR and that is to import the IBM* WSRR certificate and keystore. You can find more specific information in the IBM* Redpaper, Integrating WebSphere ServiceRegistry and Repository with WebSphere DataPower, on how to extract these from the IBM* WebSphere instance that is hosting the IBM* WSRR application. We will put these into an Intel SOA Expressway Security Package which we’ve named WSRR. Notice these items are under Application Configurations on the Configuration tab. In Intel SOA Expressway, an Application Configuration is the container that allows for settings that apply to the active Application Configuration which can be used as part of a ‘develop and deploy’ lifecycle which we will cover in a later blog post. The System Configuration holds settings that apply no matter what Application Configuration is active.

Finally we will deploy our application bundle to the configuration:

Now we get the structure of our application in the left side hierarchy of the Intel SOA Expressway web interface. Notice there are two Invocation Agents, one for our WSRR lookup and another for the Calculator web service call. Also notice that the WSRR lookup is specified [HTTPS.]

Since IBM* WSRR is configured by default to require mutual authentication for [HTTP] the certificate and keystore will need to be presented at the time of connection by the invocation agent. We will apply the WSRR named Security Package to the Invocation Agent that will make the runtime calls to IBM* WSRR. Notice that you can specify items like destination IP address and TCP port as well as a hardware interface to bind to for the network communication.

Once these steps are complete we can save our (and activate if necessary) our Configuration on the Intel SOA Expressway. Now we’re ready to test our deployment. You can do so with any tool that can post SOAP messages to the IP address and port specified on the Input Servers section. Here’s a sample SOAP message for the Add operation we’ve exposed on Intel SOA Expressway:

And the expected response:

If you’d like to try this on your own evaluation copy of Intel SOA Expressway you can register here for a download. If you don’t have IBM* WSRR and would like to try this integration you may also register for a evaluation session on the Amazon cloud where we have this and many more scenarios you can build and run on a personal instance provisioned for you there for a day. Stay tuned for more blogs that will continue to build on the key tenets of SOA governance and how to put them into practice using Intel SOA Expressway and other SOA solutions in your ecosystem.

*Other names and brands may be claimed as the property of others.
GDCeu'10: the question I was never asked about nulstein

Posted: August 13th, 2010, 11:15am MDT by Jérôme Muffat-Méridol (Intel)

Long lost feeling of my video game development days... It's friday evening, I'm the last one at the office, putting the endless finishing touches to the presentation I'm doing on tuesday. Code has gone through many checks, and still had missed the usual "if there is a space in the project's path, build breaks". Presentation's slides, although ready for weeks, have received these little extra streamlining bits: one here, one there, prune, refine, careful like with a bonzaï. And it's all finally ready, just hope the public will like it too !

While preparing this, I've been realizing that in the couple of years I have been working on this, between this version and the previous one, not one person has asked me "why is it called nulstein?". It feels odd because most of the things I have worked on in the past, started without a name (or started with a name like "next-gen uber-animation-system de-la-mort-qui-tue") and the need to give them a meaningful name came as they grew, and once the project had a name, that name became like a banner of war, it would help people gather and join forces around a motto. And newbies would come by and ask "why is it called UFO?" (because it is our "Unified File Organisation", (and that's another story)).

Okay, because now you finally ask, what does nulstein mean ?

It means a lot to me, it helps me keep the right focus for this project, and here is the motto:
"if it is rocket science, you need Einstein. If not, nulstein should do"
Standing on the shoulders of this particular giant, it is easier to try and build something that is as simple as possible (but not too much so)...

If you're at GDCeu, don't hesitate to come and have a chat, we can discuss parallelism, banners of war, naming things you care about and the odd habbit of finishing packaging a project on the end of a friday after everybody has gone and everything is nice and quiet.
GDCE2010: How DirectX 11 and Intel TBB help to multi-thread your games

Posted: August 13th, 2010, 9:16am MDT by Michael J Huelskoetter

In three days Game Developers Conference Europe 2010 in Cologne will start and several hundred game developers and other folks from all over Europe will listen to dozens of tech sessions. Four of them will be held by Intel Software Engineers who will have interesting things to tell. About two of those sessions I've blogged already (session #1 and session #2), and today's blog post will cover both Tuesday's presentations (17 August), which have to do with multi-threading your games.

The first presentation will start at 9:00 am, is 50 minutes long and will be held by Jerome Muffat-Meridol (yes, a French guy). Jerome will talk about the opportunity to multi-thread your games by using the appropriate DirectX 11 features. The name of the session: "UFO Invasion: DX11 and Multicore to the Rescue" which can be visited on 4th floor at "Nördliches Sitzungszimmer".

With Jerome's help you will learn how draw calls can be submitted to several threads, which will parallelize your games better and more efficiently. And because seeing is better than hearing Jerome will show how you can implement a multicore optimized game with the help of Nulstein, a previously published demo game engine. Nulstein will help to distribute the game code to several tasks which will help to run the multi-threaded game optimally balanced on an n-core system.

Jerome will also show one way to leverage DX11 deferred contexts, even when support from the graphics driver is not available. In summary you will learn how multi-threaded games will scale on n-cores, how you can implement multi-threaded code more efficiently and how to use Intel profiling and debugging tools properly.

Tech session number two on Tuesday will take place from 2:20 to 3:10 pm at "Nördliches Sitzungszimmer" (4. Stock), too. Mister Mario Deilmann from Intel will talk about Intel Threading Building Blocks and how this runtime library can help you to multi-thread your games with thread-save lambda functions and other parallel programming stuff. Moreover Mario will show which Intel analysis tools can help you to profile your applications which is crucial to multi-thread your games and thus take advantage of multi-core architectures.

Mario will also present the current release of Intel TBB and demostrate how the new features like the enhanced task scheduler and memory allocator, improved lambda C++ 0x support and enhanced compatibility for Visual Studio 2010 and related components.

The good thing about it: you will learn about the interesting topics which Steve, Leigh, Jerome and Mario will talk about as we will live-twitter and live-blog from GDCE 2010. And we will shoot interesting video clips with all four Intel guys, too, who will speak about their tech sessions in detail. So, see you next week - either in Cologne or here on this blog!
FTP uploads validation with Intel® SOA Expressway

Posted: August 13th, 2010, 12:00am MDT by Anton Luht (Intel)
If you are a web services developer and you build a new SOA system, you probably choose HTTP as a transport. However, sometimes you should support legacy systems that use other protocols for information exchange, for example, FTP. There are several technical nuances to be addressed in this case.
1. If client sends data over [HTTP,] you may analyze it and reply with error code if it’s incorrect. If client uploads data by FTP, how will you notify him that you can’t accept it?
2. The incoming directory for clients’ uploads may contain bad data – you should add a verification code to file processing job.
Both problems can be solved using SOA Expressway (www.dynamicperimeter.com), better, more flexible implementation of the XML Gateway pattern.

You can set SOA Expressway as an FTP server that analyzes files uploads and passes through only correct data. Clients will receive error messages if validation fails.

This instruction may seem long because every click is put as a separate item, but in fact coding of this application will take less than 10 minutes. Launch Services Designer and let’s start.

Create an empty Intel SOAE Project. Create an empty SOAE workflow in it. Add ‘Receive’, ‘Invoke’, ‘Reply’ activities to the workflow. Let’s configure them one by one.

Receive

Choose Protocol = ‘FTP’, mode = ‘Listening’. Choose port number you want to use and put it after host name in ‘Host’ field – I use port 2121

Invoke
- In ‘Advanced: Message structure’ section, ‘Request Data Structure’ subsection check ‘Enable proxy pass through for message request’
- Request Message Data – choose ‘Receive’ as data source
- Select Protocol = FTP and Invocation Agent Mode = ‘FTP command’
- Set host name to a real FTP server you’ll use as a backend
Reply
- In ‘Advanced: Message structure’ section, ‘Request Data Structure’ subsection check ‘Enable proxy pass through for message request’
- Set response message data source to ‘Invoke’
The simple FTP pass through application is ready. You can make sure that it works. Start your Intel SOA Expressway instance. Select your project in the navigation panel. Open Service Designer dialog: Run -> Deploy as -> Intel SOAE Application. Enter SOAE host name in the dialog and press ‘Deploy’. After application is deployed you can log in to your SOAE host using FTP client. Use your backend FTP server user log in and password. You can browse directories, upload, download and delete files – SOAE management console will show a number of successful requests.

Now let’s modify workflow to validate uploaded files against schema. To do this we’ll analyze FTP commands – if they are store commands ‘STOR’ or ‘STOU’, then message body is validated.

First let’s add the schema to the project:
echo.xsd
<?xml version="1.0" encoding="UTF-8"?> <schema xmlns="http://www.w3.org/2001/XMLSchema" targetNamespace="http://example1.org/example1" xmlns:tns="http://www.example.org/echo"> <element name="echo"> <complexType> <sequence> <element name="Text" type="string"/> </sequence> </complexType> </element> </schema>

Change incoming message type from ‘Binary’ to ‘Echo’. In ‘Receive’ activity properties change ‘Request data’ checkbox to ‘XML’ and press ‘Browse’ to see available types. Select type from current project and press ‘OK’.

To analyze FTP protocol data we need ‘Get Metadata’ activity – put it after ‘Receive’. Choose ‘Receive’ as the message to get metadata from

Add ‘If’ condition and put ‘XMLSchemaValidation’ into it. To edit XPath expression for ‘If’, press xpath editor icon in the table in ‘If’ properties secton. Use XML Query builder for FTP command name. The resulted XPath expression will be
$GetMessageMetadata/md:transport/md:command/md:name='STOR' or $GetMessageMetadata/md:transport/md:command/md:name='STOU'

Configure XML validation activity:
- Data to validate is ‘$Receive.body’
- Target namespace is [example1.org]
- Element name is ‘echo’
The resulted workflow should look like this screenshot:

Save the application, deploy. Log in to FTP proxy application again. Here is the file that conforms to schema:

input.xml
<ns1:echo xmlns="http://example1.org/example1" xmlns:ns1="http://example1.org/example1"> <Text xmlns="">hello</Text> </ns1:echo>

Let's try to upload this file and any text file (not conforming to schema)

ftp> put input.xml 200 Command PORT okay. 150 File status okay; about to open data connection. 226-File successfully transferred 226 0.001 seconds (measured here), 250.95 Kbytes per second ftp: 146 bytes sent in 0.00Seconds 146000.00Kbytes/sec. ftp> put input.txt 200 Command PORT okay. 150 File status okay; about to open data connection. 421 Proxy command STOR Failed, Session is terminated. Connection closed by remote host. ftp>

As you can see, the file that couldn’t be validated, wasn’t stored

Management console shows

This is the very basic application of such kind. Possible extensions are:
- do not close connection but send user-friendly error message – implemented using fault catch and reply
- transform files on upload and download
- use schema URL – if schema changes, the application will fetch and use a new one
- Using SFTP instead of FTP
Intel SOA Expressway (www.intel.com/software/soae) runtime enables multi-threading, error handling, fault recovery and other features for this application.
8 Game titles from Funkitron are now available in Intel Appup Center

Posted: August 12th, 2010, 4:41pm MDT by Gunjan Rawal (Intel)

New Page 1

read more
Report on Film/Entertainment Industry in California and Upcoming Digital Art Events

Posted: August 12th, 2010, 3:31pm MDT by Audri Phillips

When I went to what seemed like a much smaller Siggraph this year, (but that is another blog) a number of people were talking about the film/entertainment industry here in California and how industry jobs have been leaving for other states and countries for a variety of reasons. At Siggraph I was introduced to Pam Hogarth who used to head up the Gnomon School of Visual Effects and is now head of marketing for Look Effects, Inc. She told me she had read a marvelous article put out by the Milken Institute, a well known economic think tank, "Film Flight: Lost Production and Its Impact on California." I read through the article and found it documented very well the flight of film jobs from California and the tremendous cost of this to the state and the people who live in the state. It also had 10 great suggestions for luring back and keeping film jobs here. Working for many years in the digital animation, visual effects world here in Los Angeles I was particularly gratified to see, "consider implementing a new digital media tax credit to attract and retain developers of digital animation, visual" as one of the suggestions.

So I have attached the pdf file Film Flight: Lost Production and Its Impact on California of the report to this blog and encourage all to read and comment on it.

Coming Events;

1.In the future I hope to interview Paul Young . He has been curating shows of video art/experimental animation in the Pacific Design Center, 8687 Melrose Ave, Los Angeles, California. Currently up are 2 shows, Surface Tension, and Amok Stategies: the 80s Show, July 22- August 30.

2. In the Future I hope to Interview Steven Churhill, long involved with digital video and photography. He is putting on his annual Art of Photography Show. Opening Reception Gala: August 28th 6-10 pm (cost free) , Location: Lyceum theater Gallery in San Diego's historic Gaslamp Quarter.

3. J. Walt Adamczyk puts on wonderful art/animation performances of digital magic.

Gardens of Illucium: A live visual and musical performance collaboration between the Hutchins Consort and J-Walt's Spontaneous Fantasia. The performance is a ninety-minute structured improvisation which will take the audience into a virtual world of imaginary and semi-imaginary species a garden of improvised plants and mythical spices, evoking the desires for the exotic, mysterious and the slightly dangerous. As the musicians of the Hutchins Consort weave a sensuous tapestry of tonal color on their various violins, plucked strings and percussion, J-Walt will draw a computer-generated 3D virtual world populated with fantastic other-worldly flora, creating a garden of unearthly designs.

August 14, 2010 7:00 PM

The Omnicentric Universe at the Glendale community College Planatarium August 28, 7pm and 8:30 Pm

[www.johnadamczyk.com] for information on tickets and locations

4. I would also like to mention that I have a 2 minute short in the International Film Festival Ireland, September 4th -11th 2010. I won't be going, but love to hear a report from anyone who does.
So, What am I Talking About?

Posted: August 12th, 2010, 11:14am MDT by Steve Hughes (Intel)

GDC is here again (some details about what we’re doing here and more on the GDC Site). Wow, that was a fast year, it only seems like last month when I was on the booth’s there talking about Intel® Graphics Performance Analyzers (GPA), running demo’s, oh and doing a presentation on it! Well this year I’m going to be there again talking about GPA. Why?

GPA is growing in popularity amongst developers but we’ve noticed that some of you tend only to use it for last minute triage of games that don’t perform too well on ‘this’ platform or ‘that’ GPU. It’s normally a case of “Man – its slow on the xxx, I suppose we better get GPA out…” Well, we all know that fixing code and models right at the end of a dev is expensive (we’ve all had to do it, right?). The closer to the end you are the more it costs! Well, GPA is a tool that can save you a lot of the last minute miseries by helping you look for potential problem areas early in development. What I’m talking about this year is how to use GPA as a profiling tool early in in the development cycle to help you get at problems when they happen.

Also, I’ve got some info introducing GPA3.0 which is the new revision of the tool suite. There’s new features, new counters, new bits & bobs, a wider range of supported OS’s and a great new tool called ‘Platform View’, which lets you look at CPU / GPU load in whatever context you set up for it. You can use Platform View raw, but it’s best if you instrument your code with the easy to use API that comes with it – that’s when it comes into its own. More on that at the show – don’t want to spoil it by giving too much away.

I’ll be presenting at 10:10am on Monday morning so, if you’re coming along no loud noises please:) Looking forward to seeing you all there.

Steve
Optimize Your Game For Intel Integrated Graphics Adapters

Posted: August 12th, 2010, 7:42am MDT by BrianDevArch

Our compilers can only take us so far in terms of raw code performance. When it comes to graphics programming, we must take into consideration the cost of each method and whether we are implementing it to leverage the available graphics adapter features.

read more
Optimize Your Game For Intel Integrated Graphics Adapters

Posted: August 12th, 2010, 7:42am MDT by BrianDevArch

Our compilers can only take us so far in terms of raw code performance. When it comes to graphics programming, we must take into consideration the cost of each method and whether we are implementing it to leverage the available graphics adapter features.

read more
GDCE2010: How to build Games for Netbooks

Posted: August 12th, 2010, 6:35am MDT by Michael J Huelskoetter

Ok, folks, this is part three (click to see part 1 and part 2) of my pre-GDCE2010 coverage and it has a lot to do with a short preview of Leigh Davies' tech session at the huge game developers conference which will take place in Cologone, Germany from 16 to 18 August, 2010. The title of his presentation: "Building Games for Netbooks". It takes about 50 minutes, starts at 2:20 pm on Monday 16 and can be visited on 4th floor at "Nördliches Sitzungszimmer".

During his session Leigh will talk about several aspects of developing games for netbooks like smaller form faktors in terms of display and keyboard, but he will also strive crucial things like longer battery life and limited CPU power. So you'll learn how to optimize for CPU and GPU on x86 based netbooks to leverage the opportunity of selling your mobile games for 40+ million devices.

Leigh will share tips and tricks for maximizing performance, battery life, connectivity, and development on this rapidly growing platform. You'll learn how to take advantage of self-publishing business opportunities offered by the major OEM providers, Dell, Samsung, Acer and Asus. Namely he will show how you can earn money by participating in the Intel Atom Developer Program and thus being allowed to sell your mobile games through the Intel AppUp Center which is Intel's app store for Windows and Moblin/MeeGo based applications.

And if you - as an iphone and ipad developer - are lucky you will benefit from this session either as Leigh might talk about the opportunity how to port your mobile games to netbooks. And if not, stop by at the Intel booth which is part of the huge showcase at GDCE 2010. Leigh will be glad to answer all your questions there.
Intel Application Lab coming to Portland, OR on August 25

Posted: August 11th, 2010, 7:57pm MDT by Gina M Bovara

PORTLAND APP DEVELOPERS! An Intel Application Lab is landing in your town soon ...

read more
Accelerate your Media

Posted: August 11th, 2010, 11:51am MDT by Rick Puckett (Intel)

Are you familiar with the Intel Media SDK? If not, here is a great video that explains how it works and the benefits of using a single API. This is good stuff. Check it out here!
GDCE2010: "How to use Intel Graphics Performance Analyzers"

Posted: August 11th, 2010, 6:48am MDT by Michael J Huelskoetter

As I blogged already, we will go to Game Developers Conference 2010, which will take place next week from 16 to 18 August, 2010. And as usual, we will be heavy equipped with our video cam, notebooks, lights, mics and a lot more. Our mission will be live-twittering, live-blogging and live-interviewing from one of the biggest developer events of the gaming industry.

And we won't be alone as several Intel people will come to Cologne either. They will show interesting software demos at the showcase and they will talk about different topics, too. And as I promised yesterday I will give some information about the four tech sessions which you can expect from Intel during GDCE 2010.

The first presentation will be on Monday from 10:10 - 11:00 am, will be held by Steve Hughes and wears the title "PC Profiling Made Easy with Intel Graphics Performance Analyzers". Steve is Senior Application Engineer with Intel and his session will take place at "Nördliches Sitzungszimmer" on 4th floor.

Steve's tech session will cover the main features of Intel Graphics Performance Analyzers (IGPA) and how you can achieve realtime analysis of game code with minimum runtime overheads. Therefore IGPA offers different profiling views for run time tracking of system wide performance, visualization tools, visualization systems, a graphical frame analyzer, debugging tool and a tool for instrumenting your code for multithreading performance analysis.

In his presentation Steve will show how IGPA can save time and effort identifying performance bottlenecks on both CPU and GPU. This means to you as a developer that you can spend more time on the code and less time on searching annoying bugs for hours. So you can look at particular draw calls, calculate texture bandwidth and see how much time the different shader grab from the whole system. So, don't miss Steve's presentation about IGPA and what it can do for you. And when he is at the Intel booth he will show you this cool tool for free!
Intel at GDC Europe 2010

Posted: August 11th, 2010, 5:36am MDT by Khan Basher (Intel)

This is for all you game developers attending GDC Europe 2010 in Cologne, GERMANY; taking place at the Cologne Congress Centre East from 16th – 18th August. This year Intel experts will be speaking at the event, they will be giving talks on the following essential technical sessions. GDC Europe will feature sessions based on a comprehensive selection of game development topics taught by industry experts (Sessions) .We will have a dedicated web page Intel at GDC Europe 2010 for all event updates, schedules including photos from the event and PPT session materials from Intel presenters. I look forward to seeing you there, either in-person or virtually online via posts & comments!
Technical sessions:
PC profiling made easy with IGPA by Steve Hughes: Tired of writing profiling code every time you work on a project while constantly battling with ever increasing data you need to track? Intel’s Graphics performance Analyzer can take the strain. And, it’s free!
IGPA 3.0 offers a range of features designed for realtime analysis of game code with minimum runtime overheads. IGPA offers 3 complementary profiling views including run time tracking of system wide performance metrics, a range of visualization and ‘what-if’ tools, visualization systems, a graphical frame analyzer, debugging tool and new for version 3.0 the ability to instrument your code for multithreading performance analysis. In this presentation we show you how IGPA, used as a profiling tool, can save you time and effort identifying performance bottlenecks on both cpu and gpu, leaving you to write the code that matters. We will also look at a few of the graphic debugging tools that can help track hard to find artifacts during a games QA phase saving valuable time without the need to specialist builds of the game.
Building Games for Netbooks by Leigh Davies: Do you keep missing the train with new mobile game platform opportunities? Millions of netbooks are waiting to run your game, and millions more are being added to the pool each year. In this session you'll learn how to optimize for CPU and GPU on x86 based netbooks to leverage the opportunity. We'll share tips and tricks for maximizing performance, battery life, connectivity, and development on this rapidly growing platform. You'll learn how to take advantage of self-publishing business opportunities offered by the major OEM providers, Dell, Samsung, Acer and Asus, and a lucky attendee will win a netbook they can use to get their game running for this exciting new game platform!
UFO Invasion: DX11 and Multicore to the Rescue by Jerome Muffat-Meridol: With DX11 comes the ability to submit draw calls from several threads, which brings the promise of a fully parallel and scalable game loop one big step closer. We will use nulstein, a demo engine published previously, to implement a multicore space battle. We will then profile the code and look at how the engine breaks the work down into tasks and how this load gets balanced. We will then move on to show one way to leverage DX11 deferred contexts, even when support from the graphics driver is not available. Full source code to be made available.
Turbo charge your game with Intel Threading Building Blocks by Mario Deilmann: Introduce parallel algorithms in your game applications and stay competitive. With new and updated parallel programming models and parallel performance analysis tool Intel will help you to prepare your applications to take advantage of the multi-core architectures of today and tomorrow.
This talk will introduce the new version of the award-winning open source Threading Building Blocks runtime library that simplifies the writing of multithreaded applications. This presentation will talk briefly about then benefits of threading building blocks in game engines, about the new features of TBB 3.0 along with new feature of our parallel Profiling tools. It has been never been easier to get your game engine parallelized!
GDCE2010: tech session information and more

Posted: August 11th, 2010, 4:05am MDT by Michael J Huelskoetter
In less then one week - exactly from 16 August, 2010 one of the leading developer conferences of the gaming industry will start in Cologne, Germany, Europe: Game Developers Conference Europe 2010. And as for many years now Intel will be part of this huge show presenting why it‘s so important to optimize your gaming titles for Intel architectures and platforms.

In order to show the different topics related to game developers in an optimal way Intel will sponsor GDCE 2010 once again as one of the main sponsors including several tech sessions and their own demo booth where you will see and learn a lot about developer tools like Intel Graphics Performance Analyzers - live demo included.

The four tech sessions will take place on Monday and Tuesday and will cover the following topics:
- Monday, 10:10 - 11:00 am: PC profiling made easy with Intel Graphics Performance Analyzers with Steve Hughs who will probably show the live demo at the Intel booth again.
- Monday, 2:20 - 3:10 pm: Building games for netbooks with Leigh Davies
- Tuesday, 9:00 - 9:50 am: UFO invasion: DX11 and multicore to the rescue with Jerome Muffat-Meridol
- Tuesday, 2:20 - 3:10 pm: Turbo charge your game with Intel Threading Building Blocks with Mario Deilmann
The four Intel experts will be available before and after their tech sessions so that you can ask all your burning questions regarding game development on Intel architecture. Well, it will be worth it coming to Cologne!

BTW: If you wanna know what the different tech sessions will be all about you should visit this blog the next days and the next week also as we will cover the sessions and more by twittering, blogging and with video interviews live from Cologne. So, watch this space!
Authenticating signing certificates from XML Digital Signatures with Intel® SOA Expressway

Posted: August 10th, 2010, 4:38pm MDT by Pete Logan (Intel)
Okay, this is my first post and I want to jump straight in with a neat little method of authentication which is often used when Intel® SOA Expressway is deployed as a Service Gateway. It also gives you the ability to be agnostic to whether you’re dealing with SOAP or REST XML patterns in your messaging.

Generally in these blogs I’m going to assume a little bit of familiarity with Intel® SOA Expressway and Intel® Services Designer but if you’re curious to know more or a noob then drop me a comment and I’ll fill you in on the extra detail.

In this situation we are dealing with a non WS Security XML Digital Signature such as a detached or enveloped type. WS Security signatures have authentication built in to the verification policy and are dealt with already in the quickstarts which come with Intel® SOA Expressway. Check out the Dynamic Perimeter micro site to get more info on these capabilities and to get a copy of SOA Expressway yourself.

When you use one of our inbuilt extension functions like soae-xf:verify-x509-enveloped-signature it checks the digests are correct etc. but does not go on to see whether SOA Expressway trusts the certificate of the message signature. To do this we must add a BPEL action to check the chain of trust which has been setup in the security config.

- To do this, first drop an AAA (Authentication, Authorization & Access) action into your workflow. The tokens I'm using here refer to the inbuilt default security config provided with SOA Expressway. Substitute these for your own tokens where necessary when you deploy on the runtime.. The AAA action will need a message to be passed to it. The inbound request will do.

- Create a policy for this AAA action with the following parameters set:
- Extract Identity
- Identity source: X.509 Certificate from workflow
- Certificate attribute: Full certificate
- Authenticate Identity
- Authenticate using: X.509 Certificate Chain of Trust
- Authentication policy, token name: demo-message-level-authentication-policy
- CA Path: selected
- Security configuration, token name: demo_ca_path
- Update the policy back in the AAA action properties pane. You will now need to pass a parameter specifying the Source Identity of the X.509 Certificate. This can be extracted from the message using XPath similar to this:

$Request.body//ds:KeyInfo/ds:X509Data/ds:X509Certificate

The above works for our inbuilt security but to change over to your Certification Authority you will need to have added your CA certificate into the Security Config in the SOA Expressway runtime web interface.

If there's a failure of the authentication the following fault will be generated:

<soae-fault:checkPkiCertificateChainOfTrustFault xmlns:soae-fault="http://www.intel.com/soae/bpelFault-2009a/">
<faultString>Error in checking certificate chain of trust</faultString>
<details>
<policyName>Policies/EnvSigVerify</policyName>
</details>
</soae-fault:checkPkiCertificateChainOfTrustFault>

So why is this a neat trick I hear you ask? SOA Expressway isn’t enforcing you to deal with the authentication in either a SOAP or a REST way which some XML Appliances and Java Frameworks might. Just change the XPath and you can be extracting a detached digital signature from the SOAP Header. In fact I’ve taken this method from a mixed SOAP/REST workflow I developed for a financial transaction web service at a bank which used SOA Expressway as a security gateway and also for runtime governance. More on that workflow later….
Visualize This! 36 - Game Programming Gems Drag physics in game development

Posted: August 10th, 2010, 10:56am MDT by Arti Gupta (Intel)

Enclosure: [download]

Welcome to another episode of Visualize this! the show where we talk about game development.

My guest is BC (Charlie) Rasco one of the authors of Game Programming Gems 8th edition. Charlie is President of Smarter than you software This is the second interview in a series I am conducting speaking with some of the authors of this book about their areas of expertise and their experience with contributing to this book.

Download the high quality MP4 video file (large).

Questions :
1. Tell us about your background and your role in the GPG book
2. What is drag physics and why is it important? Where can it be used in games?
3. This applies to casual games too like Golf globe, tell us more about this game. (Do you have a video of the game to talk through this question?)
4. What are the 2 different types of drag models?
5. Is one better than the other? Where do you recommend using one or the other?
6. What are the challenges in implementing drag modeling

I am always looking for community feedback and questions. You can email them to visualizethis@intel.com or provide on twiter @artigupta

You can watch Visualize This! live alternate Tuesdays at noon Pacific on Intel Software Network TV, our new 24/7 interactive video channel. Come chat with us, or browse the On Demand section to see past episodes of our shows.
The Game Creators Launch Best Netbook Game Contest

Posted: August 10th, 2010, 9:48am MDT by Bob Duffy (Intel)

For $5K and bragging rights
Apparently killing zombies & shooting aliens on a netbook could be better. So The Game Creators and Intel have teamed up for a competition to create the best netbook game using tools and software available from The Game Creators. To enter this contest go to The Game Creators contest page

read more
The Game Creators Launch Best Netbook Game Contest

Posted: August 10th, 2010, 9:48am MDT by Bob Duffy (Intel)

For $5K and bragging rights
Apparently killing zombies & shooting aliens on a netbook could be better. So The Game Creators and Intel have teamed up for a competition to create the best netbook game using tools and software available from The Game Creators. To enter this contest go to The Game Creators contest page

read more
Multi-Core Faculty Workshop in China: The 5th Year!

Posted: August 10th, 2010, 2:07am MDT by Selwyn H. You 游骅 (Intel)

On July 29th and 30th, 2010 faculty workshop of Multi-Core was held at Tsinghua University, China, indicating the event just makes its 5 years' history. Ever since 2006, faculty workshop of Multi-Core have been as a major academic event where Intel can share the leading-edge technology with the academic community.

After these years of continuous efforts, Parallelism is now well adopted in the Chinese curricula. Rather than just Programming Fundamental type of classes like threading APIs, Chinese professors also teach the MC technology in other subjects where it may apply. Take a look at the proposals for PRC MoE-Intel model classes, a program through which Intel sponsors to cultivate technology adoption in university curricula, the submitted MC related classes cover Architecture, Compiler, Operating Systems and Software Engineering, in addition to the Programming techniques. With all these years of accumulation, over 40 thousand students were trained in 100 plus universities. As a major contributor to the achievement, the annual faculty workshops play an important role. Each year, there will be new content either from Intel technology or response to the request posted in the previous workshop. And the target audience is the teaching faculty from fourty-ish key universities that is expected to be the quick adopters and influencers to other universities.

With the aforementioned philosophy, the main theme of Tsinghua MC faculty workshop is application examples of Parallelism and its design patterns. The workshop started with an overview session to set the stage and sync with the audience on the basic techniques used. Then example of using Parallel Studio was given. The first new content introduced at the workshop is the Algorithm Parallelization with OpenMP, in which module methodology of parallel programming were examined and practised through OpenMP work sharing constructs. The notion is try to fill the gap between the computing theory and the students hands-on skills. Besides, examples from different application fields like Dynamic Molecular, Game Application Threading Methodology (with Win32 API, TBB and OpenMP) were the major demostration showed to the audience for the corresponding teaching subjects. Lastly, a module Parallel Programming Design Patterns with Examplesdelivered by ACM education council member Michael Wrinn wrapped up the whole workshop with more systematic summary for the faculty and students to Parallelism. As a quick information, an invited speaker Colt Gan gave An Introduction to Cilk at the workshop as well as an example of new threading models.

The workshop finished with all planned goals reached. The attendee faculty were equipped with new content to adopt in their further curricula development. Before the close of the event remark, I would share one note I took at dinner table conversation. There are notable amount of colleges teaching programming languages of managed run-time, i.e., Java. And they are interested in exploring the similar opportunity in Java as it is to C/C++. I've recommended them to go and download Introduction to Parallel Programming with Java from ISE Moodle and start thinking of broader topics that had interested the both faculty and students.
New Mesh Agent with Windows Prompt Fix

Posted: August 9th, 2010, 11:06pm MDT by Ylian Saint-hilaire (Intel)

Tonight I just released a new version of the Mesh Agent in the wild. Version v0.0.91 has a few more bug fixes but the most noticeable one is working access to the Windows Command Prompt from within the MeshCentral web site. This makes use of the Javascript VT100 terminal that I have been working on a few weeks ago. In the past, the Mesh Agent compiled for Linux would work great, but attempting to shell to the command prompt on Windows would be quite unstable.

I was not looking forward to fixing this instability since it required me to get my head back into the agent code which is tight C, but I just had to do it. Besides the Mesh Agent had not been updated for a few weeks now and it was time to work on some fixes. Most of the past two months have been spent working on the server side.

Also, a new update from Kishen Maloor, my co-worker on the mesh project. Today he completed the configuration page for setting up Twitter policies. The page is live now on MeshCentral (look for "social settings"), you can associate a Twitter account to Mesh Central but it does not do anything. The server does not Tweet to user's accounts yet, but that should come soon.

Lastly, I am going to be speaking at the Intel Developer Forum (IDF), September 13-15. We will be covering the topic of mesh networking and what it's good for. I will have a session and two labs, should be lots of fun.

Ylian
meshcentral.homeip.net
What I did on my Summer vacation

Posted: August 9th, 2010, 6:14pm MDT by Clay Breshears (Intel)
The UPCRC (Universal Parallel Computing Research Center) at the University of Illinois, Urbana-Champaign (UIUC), held their second Multicore Summer School this past July. Like I did last year, I participated as an instructor for some of the modules offered. Specifically I taught about programming with OpenMP and Intel Threading Building Blocks. Since the lab systems were using the Microsoft Windows OS, I also gave a presentation on how to use the Intel Parallel Inspector and Intel Parallel Amplifier tools to find threading errors and performance issues.

Teaching about programming with OpenMP

During the five days of the Summer School, the following topics were covered:
- Introduction to Parallelism and Multicore Technology
- Explicit Mutlithreading
- Parallelism with Java
- Refactoring for Parallelism
- Shared Memory Control Parallelism with OpenMP
- Shared Memory Control Parallelism with Intel Threading Building Blocks
- Parallel Code Debugging and Tuning
- Parallel Programming in Visual Studio 2010
- Vectorization
- GPU Programming
- Special Lecture: Intel Parallel Advisor
- A Taxonomy of Parallel Programming Models
The majority of the above modules were presented by University of Illinois faculty, many of them internationally known for their work in parallel programming. Phil Pennington and James Rapp from Microsoft delivered the lecture and labs for using Microsoft Visual Studio 2010. The students came from all across America and from different points around the world (e.g., Pakistan, Australia, Brazil, Ireland).

The course lectures were streamed live for those students that could not join us in Illinois. The videos were also recorded for those off-site participants that could not conveniently attend the lectures in real-time. Also, the taped lectures were slated to be used at a sister site in Singapore in order to conduct the same course without needing to transport all of the module instructors halfway around the world.

Hands on lab exercises were offered to students for the programming modules. The labs were well attended by participants that were on site at UIUC and the machines were available to all off-site students to give them the chance to work on the labs and practice what they had seen in the lectures.

Helping work out a programming problem in the lab.

During live lectures, a student moderator took questions from offline students as they watched the video feed. An online forum for each lecture and lab was set up to allow students to keep in touch with the course instructors and lab assistants when they were not lecturing. If a question came up and no one was available to answer the question, the student was off-site or the student had returned to their room for the night, she could post a question on the forum. Other students, the student lab assistants, and the instructors could chime in with an answer. This was a most valuable interaction method for the off-site students.

Everyone I talked to said the whole experiences was very valuable and they learned quite a bit. For some pictures that were taken during the week (and where I got the pics included in ths post) click here. I've always said that this week-long course is like a Whitman's Sampler where you can get a taste of many different types of parallel programming and the issues involved. After you've had some practice, you can delve deeper on that specific topic or methodology you find to be most beneficial for your needs.

Plans are already afoot for the 2011 Summer School. If you want a quick introduction to current issues and methods for parallel programming on shared memory architectures, you will want to check out the offerings for next year. Since I'm in town already, I should be back for a couple modules. I hope to see you there, too.
Kaltura's Michal Tsur on Open Source as a Business Strategy

Posted: August 9th, 2010, 11:58am MDT by Lisa Hoover

In the world of emerging software technology, it can sometimes seem like there's nothing new under the sun. Kaltura, who claims to be the first the first open source online video platform, recently released Kaltura Community Edition 2.0 that supports a full set of online-video mastering tools, widgets, plugins, and applications meant to be run behind the publisher's firewall. To find out what role open source plays in Kaltura's business strategy and what challenges the team encountered along the way, I caught up with its President and Co-Founder, Dr. Michal Tsur.

According to Tsur, making open source an integral part of Kaltura's business strategy brings several benefits to the table. " Open source allows us to build an ecosystem of innovation around our platform and business. We can build on and incorporate existing projects, and also include add-ons developed by others to our platform.

"Open source has allowed us to implement a horizontal strategy. Rather than focusing our platform solutions on a particular vertical (e.g. media and entertainment, education, enterprise, government), our openness allowed us and our partners, to easily adapt our core platform services to all of these verticals. This way, we provide solutions to Media companies, universities enterprises and government."

Kaltura had its work cut out for them beyond just creating a good video platform. "The main challenge is that of building a profitable company around free and open software, as well as building a true strong and involved developer community, " says Tsur. The company is meeting those challenges head on by "building an ecosystem of network services on top of our free software that has significant distribution [and] adopting a dual licensing strategy, which allows us to offer a commercial license to our software, with full maintenance and support." The company maintains a strong user community on its Web site and also offers a Software-as-a-Service (Saas) option for customers who prefer not to self-host.

In keeping with its dedication to use open source software, Wikipedia currently uses Kaltura's technology to power its video needs. Universities and government agencies are choosing it as a cost-effective way to produce and distribute video in-house. Whether businesses to use Kaltura's products due to its open source licensing or because it's a less expensive alternative to commercial video platforms, the message is clear. An open source business strategy is worth considering when you're developing products and services for mass appeal.
Practical Application of Data Convergence

Posted: August 9th, 2010, 11:50am MDT by Joe Welsh (Intel)
A typical Healthcare Information Exchange (HIE) accepts data from an array of disparate sources. Often the data it accepts is semantically and syntactically altered by a providing system to satisfy interfacing requirements. However, there are also cases where data from different sources need to be properly merged before reaching the HIE's interface. In a recent proof-of-concept with Intel's SOA Expressway for Healthcare I completed with an HIE provider, I demonstrated how this was done for Lab Results.

The use case called for SOA Expressway to accept an HL7 v2 Lab Result (ORU) and merge into the message contents of files on one or more remote FTP servers. The Lab Result contained specific references to the files that were required. Success criteria for SOA Expressway's proof-of-concept were defined by the following:
1. Accept a Lab Result via HL7 v2.x
2. Synchronously retrieve the contents of a file from a reference in the result section.
3. Replace the FTP file reference with the content of that file.
4. Repeat for each FTP file reference
The Application

The below application was built with SOA Expressway's Services Designer, a code-less graphical based workflow designer that runs as a plug-in to the Eclipse Integrated Development Environment. The process yielded a WS-BPEL based application that was deployed and run on SOA Expressway for Healthcare.
1. The Receive step is configured to accept messages over the MLLP protocol used for HL7v2.
2. The HL7_XML step creates an XML representation of the HL7 v2 message utilizing a built-in universal HL7v2 parser capable of converting the most commonly used HL7 v2.1 - v2.6 messages to XML.
3. The For_Each_OBX-5 sequence iterates through each result segment of the message and:
  1. Extracts the FTP URL from the result segment .
  2. The ftp_session_id creates a unique session id to be used for each file retrieval
  3. FTP_Login creates an FTP connection utilizing the ftp_session_id and FTP URL from the steps a and b.
  4. FTP_Retrieve retrieves the contents of the file specified in the FTP URL.
  5. FTP_Quit terminates the FTP Session.
  6. replace_OBX_Value replaces the FTP URL in the current result segment and replaces it with the contents of FTP_Retrieve (file contents).
4. The HL7_XML_Serialize serializes the HL7_XML back to HL7 v2.
5. The Reply step replies back to the sender with the augmented HL7 v2 message that was serialized in the previous step.
Although this application simply sends back the augmented Lab Result, future applications would forward this to an actual HIE.

Benefits

In other integration appliances (such as an ESB, etc.) this synchronous application is typically not possible without the employment of other outside resources, scripts, or programs. Even if those appliances can manage synchronous FTP transactions, can they dynamically assign FTP credentials required for each file retrieval? How easily can they augment the original HL7 data with the file content? Using SOA Expressway I was able to do this easily within minutes.

Additional Use Cases

Although I plan on sharing more uses cases I am involved with in the future, you can check out additional use cases right now! These use cases not only showcase SOA Expressway as an integration appliance, but as a Service Gateway, for SOA Edge Security, for Runtime Governance, a BPMS id Broker, Cross Domain Sharing, as a Cloud Gateway and much more! For additional information please see:
Parallel Patterns in Seismic Duck – Part 3 (Vectorization and Tiling)

Posted: August 7th, 2010, 11:08pm MDT by Arch Robison (Intel)
This blog is part three of four about how I applied parallel patterns to Seismic Duck. Part 1 covered background material and overall parallelization strategy for the game. Part 2 covered threading. This part covers vectorization, tiling, and wide halo. Part 4 covers bookkeeping details in the real code.
Vectorization
I'll describe vectorization first. The kernel of interest is:
```
        for( i=start[k]; i<finish[k]; ++i )     // Loop over rows in chunk k
            for( j=1; j<n; ++j ) {
                Vx[i][j] += (A[i][j+1]+A[i][j])*(U[i][j+1]-U[i][j]);
                Vy[i][j] += (A[i+1][j]+A[i][j])*(U[i+1][j]-U[i][j]);
                U[i][j] += B[i][j]*((Vx[i][j]-Vx[i][j-1]) + (Vy[i][j]-Vy[i-1][j]));
            }
```
A Core-2 core can generally operate on 4-element vectors just as fast as it can operate on scalars. Thus scalar code wastes 3/4 of the machine's capability. The kernel is trivial to vectorize. Let X[i:4] denote a four-element SSE vector, starting at subscript i. In other words, X[i:4] is the quadruple (X[i], X[i+1], X[i+2], X[i+3]). To vectorizing this kernel:
- Replace the scalar operations with SSE vector operations
- adjusting the stride of the j loop index to loop over SSE vectors instead of scalars
The vectorized code looks like this conceptually:
```
        for( i=start[k]; i<finish[k]; ++i )     // Loop over rows in chunk k
            for( j=1; j<n; j+=4 ) {
                Vx[i][j:4] += (A[i][j+1:4]+A[i][j:4])*(U[i][j+1:4]-U[i][j:4]);
                Vy[i][j:4] += (A[i+1][j:4]+A[i][j:4])*(U[i+1][j:4]-U[i][j:4]);
                U[i][j:4] += B[i][j:4]*((Vx[i][j:4]-Vx[i][j-1:4]) + (Vy[i][j:4]-Vy[i-1][j:4]));
            }
```
The vectorization is legal because afterwards, the updates of Vx and Vy still use the old values of U, and the updates of U still use the new values of V. Note that allowing multiple iterations to run concurrently using threading would not be safe, as explained in part 2. The loop thus demonstrates the the point that not all vectorizable loops can be multithreaded, at least without further transformations, e.g. the ghost cell pattern covered in part 2.

The beta version of the Intel 12.0 C++ compiler actually supports the [j:4] array syntax. It's really convenient to use. Alas I was developing Seismic Duck without that support, so I resorted to SSE intrinsics and macros. The macros look like this:
```
        #define CAST(x) (*(__m128*)&(x))    /* for aligned load or store */
        #define LOAD(x) _mm_loadu_ps(&(x))    /* for unaligned load */
        #define ADD _mm_add_ps
        #define MUL _mm_mul_ps
	#define SUB _mm_sub_ps
```
With these macros the loop body looks like:
```
        __m128 u = CAST(U[i][j]);
        __m128 a = CAST(A[i][j]);
        CAST(Vx[i][j]) = ADD(CAST(Vx[i][j]),MUL(ADD(LOAD(A[i][j+1]),a),SUB(LOAD(U[i][j+1]),u)));
        CAST(Vy[i][j]) = ADD(CAST(Vy[i][j]),MUL(ADD(CAST(A[i+1][j]),a),SUB(CAST(U[i+1][j]),u)));
	CAST(U[i][j]) = ADD(u,MUL(CAST(B[i][j]),ADD(SUB(CAST(Vx[i][j]),LOAD(Vx[i][j-1])),SUB(CAST(Vy[i][j]),CAST(Vy[i-1][j])))));
```
It's efficient ugly non-portable vector code. I'm hoping that other compilers adopt the array syntax so I can write efficient beautiful portable vector code.
Tiling
Vectorization alone does not improve performance of the kernel. It slams it harder against the "memory wall". The "memory wall" refers to the limit on memory bandwidth. Reducing consumption of memory bandwidth becomes critical. Parts 1 and 2 discussed the importance of the ratio C (Compute density). It is defined as the ratio of the number of floating-point additions per memory reference. Now I'll describe how raise the value of C multifold with tiling.

The kernel as shown so far updates the wavefield for a single time step. Now it's time to bring in more context. The kernel occurs inside a loop that steps over time, conceptually like this:
```
    for( t=0; t<T; ++t ) {  // T = number of time steps per video frame (typically 3)
        replicate borders
        for each chunk k in parallel {
            for( i=start[k]; i<finish[k]; ++i ) // Loop over rows in chunk k
                for( j=1; j<n; j+=4 ) {
                    Vx[i][j:4] += (A[i][j+1:4]+A[i][j:4])*(U[i][j+1:4]-U[i][j:4]);
                    Vy[i][j:4] += (A[i+1][j:4]+A[i][j:4])*(U[i+1][j:4]-U[i][j:4]);
                    U[i][j:4] += B[i][j:4]*((Vx[i][j:4]-Vx[i][j-1:4]) + (Vy[i][j:4]-Vy[i-1][j:4]));
                }
```
With the loop structure above, each iteration of the t loop has to reload Vx, Vy, and U from memory. If the t loop could be changed from being the outermost loop to being the innermost loop, the reloads could be avoided, because each iteration would reuse values cached by the previous iteration. But naively permuting the loops delivers wrong answers, because updates would use incorrect values.

Ignore the "for each chunk" loop for now. I'll come back to that in the next section. For now, consider the other three loops. They are an abstract loop over points in space-time with coordinates (t,i,j). The constraints are that point (t,i,j) must be updated:
- after update of point (t-1,i,j) (required to preserve dependencies across time)
- after update of points (t,i-1,j) and (t,i,j-1) (required to update U correctly)
- before update of point (t,i+1,j) and (t,i,j+1) (required to update Vx and Vy correctly)
The tiling will update the points in groups. Each group is a rectangular subset of points, called a tile. A tile is updated using two nested loops as shown in the vectorized code, but i and j range over the tile instead of the entire spatial grid. An additional outer loop sequences the tiles.

Picture the kernel as a problem in tiling a floor. The floor runs along the i and j axes. The t axis is vertical to the floor. The floor must be tiled T levels deep for each video frame. T is typically 3 in Seismic Duck. Each tile of size 1×7×112. That is, each tile is:
- 1 unit thick along the t axis,
- 7 units thick along the i axis, and
- 112 units along the j axis.
Why such a long skinny tile and where did the 112 come from? The answer is that the tiles are actually square, when measured in cache lines. It's cache lines that count, because they are the quantum of information transferred between memory and the CPU. A cache line is typically 64 bytes on my intended target hardware, and I'm using single-precision floating-point. So that's 16 floats per line. The 7×7 dimension in cache lines works out to be about the right size. I chose the size by a back of the envelope calculation (based on the size of the L1 cache) and then did some experiments.

Tiles can be cut into smaller tiles if necessary, particularly when working around the edges of the grid. Part 4 will way more about this. The previous constraints on the order of updating points apply similarly to tiles. A tile can be laid at level t only if:
- all the area under it is tiled to level t-1,
- its north and west sides will not be exposed,
- its south and east sides will be exposed.
Another way to word the constraints is from the viewpoint of an ant crawling over the tiles:
- No overhanging tiles allowed.
- If an ant crawls north or west, it must never go down.
- If an ant crawls south or east, it must never go up.
Below is a picture showing both legal and illegal partial tilings. The three levels of tiles are distinguished by different colors.

The red X marks tiles that violate one or more of the constraints.

There is one more thing to model: the cache hardware. Laying down a tile corresponds to performing a calculation on data that must be in cache. Each tile is a 7x7 grid of cache lines. Call a line hot if it is in cache, and cold if it is out of cache. If a cache line is not touched, it cools until it becomes cold. A cache line can be reheated (brought back into cache), but that takes precious time. These effects add a constraint to the tiling exercise, because the computation of points in a tile depend on nearby points in space. When laying a tile, the area under and close to the new tile must be hot.

Laying a complete layer before doing the next layer is inefficient because each time a tile is laid, the area until it has grown cold. It's far better to lay a tile on top of a hot tile, ideally the one laid immediately earlier. A good pattern is to lay each tile almost on top of the previous tile, but shifted north and west one unit to meet the aforementioned "ant constraints", until the stack of offset tiles is T levels deep. Then lay another stack immediately east of this stack. Once a row of stacks is completed, do the next row.

The pattern looks tricky around the edges of the floor, but there is an easy way to deal with that. Imagine that we do not care if a tile goes beyond the floor boundary, and the overhang constraint does not apply to beyond the floor. Then it's just a matter of starting the pattern beyond the floor, and cutting off portions of a tile that extend beyond the floor.

Below is an animation of the tiling sequence for a small 23x16 floor with 7x7 tiles.

Note: I wrote the animation by hand using GIMP, frame by frame. I now greatly appreciate the effort artists put into hand-drawn animations!

With the typical depth of 3, the tiling pattern almost triples the compute density. I say "almost" because I may not be getting perfect reuse around the edges. But it's close enough. Some programs sequence the stacks more elaborately, such as zig-zagging diagonally or recursively, in order to exploit multiple levels of cache. The simple pattern I used works well for Seismic Duck because the outer level cache (e.g. L2 cache on a my system) is big enough to hold the cache lines that are reused between rows of stacks. T

The final loop structure looks like:
```
    for each video frame do {
        replicate chunk borders widely // See next section
	for each chunk k in parallel {
	    for each tile z in chunk k, in tiling sequence order, do
		for each i in z do
		   for each j in z do {
                       Vx[i][j:4] += (A[i][j+1:4]+A[i][j:4])*(U[i][j+1:4]-U[i][j:4]);
                       Vy[i][j:4] += (A[i+1][j:4]+A[i][j:4])*(U[i+1][j:4]-U[i][j:4]);
                       U[i][j:4] += B[i][j:4]*((Vx[i][j:4]-Vx[i][j-1:4]) + (Vy[i][j:4]-Vy[i-1][j:4]));
		    }
```
Part 4 will say more about implementing the tiling sequence.
Wide Halo
Note that I added the word "widely" to the replication step. Because the tiling sequence advances a chunk T timesteps instead of one, it is not enough to copy just the immediate border points. Instead, a T-point wide border has to be copied, and the space to be tiled is not a rectangular prism in (t,i,j) space, but instead is a frustum with a rectangular base in the (0,*,*) plane, and walls that slope 45 degrees. The top surface of the frustum in the (T-1,*,*) plane. The top surface is the chunk's contribution to the final computation. The bases overlap by a region T points wide. The overlapping portions of the frustums correspond to redundant calculations. See the section titled "Wide Halo" of the Ghost Cell Pattern paper for more on this technique.
Summary of Vectorization and Cache Optimizations
Vectorization quadruples the calculations per instruction, making memory bandwidth the bottleneck. Tiling in space-time reduces consumption of memory bandwidth. Doing so requires the wide halo pattern.

The tiling involves some complex bookkeeping. Boundary condition physics makes it even more complicated. Part 4 will describe how I dealt with the bookkeeping without going mad.
Updated Device Builder for UPnP Technologies

Posted: August 6th, 2010, 4:03pm MDT by Ylian Saint-hilaire (Intel)

I just updated the Developer Tools for UPnP Technologies. It's now at version v0.0.38, as always it's open source at [opentools.homeip.net] . For people that already have a previous version of the tools installed, the update should be coming using the auto-update system.

This time around I fixed up the support for embedded devices in the C generated code. The Developer Tools for UPnP Technologies has a few interesting tools, but the best one if Device Builder. You give it a device description and it generates you full C stacks that can immediately be compiled in Windows and Linux. UPnP supports a thing called embedded devices where you can have one or more devices embedded within another device. In all, it shows up as a device tree on control points. This is especially useful if you have a composite device. For example: A AV media rendering device along with a AV media server all in one.

In the past few months, I have done a major upgrade of the UPnP code, bringing it up to speed with the latest static code analysis and IPv6 support. In doing so, I broke some of the less used features and one of them was support for embedded devices. Both device and control point sides where broken and in this release, I fixed them both.

Please keep reporting bugs!

Ylian
opentools.homeip.net
Ballview visualizes an H1N1 molecule in 3D

Posted: August 6th, 2010, 1:17pm MDT by Arti Gupta (Intel)

Ok, so my last post was about a demo at Research at Intel days. I saw another demo which caught my attention as well, so thought I would jot down my thoughts.

Intel is actively researching ways to expand scientific visualization capabilities for medical research. In this demo Intel researcher demonstrates Ballview, which uses ray tracing to accurately model the molecule with shadows and depth perception. This effort showcases research from the Intel Visual Computing Institute in Saarbrucken, Germany in collaboration with Saarland University.

It is fascinating what they have done here, in order to find a cure for H1N1 they looked at the virus molecule in 3D and found that there is a lot of empty space inside which is where the virus replicates itself. So if medical researchers can find a way to block that space the virus will not have room to grow. They have used ray tracing to accurately depict the shadows inside the virus. Pretty amazing how visual computing technology is helping medical research!

For more info on Ballview check out [https:]
How to enable 3D content to display interactive movement on the Web

Posted: August 6th, 2010, 11:41am MDT by Arti Gupta (Intel)

Some of my colleagues attended Research at Intel days, and this video fascinated me. Daniel Pohl a research scientist at Intel presented a demo on Enable 3D content to display interactive movement on the web. This effort showcases research from the Intel Visual Computing Institute in Saarbrucken, Germany in collaboration with Saarland University.

This concept is really cool, it changes how we can interact on the web and web content. Reminded me of virtual reality and virtual travel :-) The demo shows buildings in Venice and instread of getting the normal photos, what if you want to walk around in the buildings? It uses XML movement which describes the geometry and light surfaces and how the textures interact with the geometry. XML 3D is implemented using a Ray Tracer and can also render using Web GL with HTML 5.

This beta version is running on a beta verison of Mozilla FireFox. Plans are to make the XML 3D scripting language available soon so encourage you to check it out. Comments or quesitons welcome :-)
Looking to get higher performance on NUMA-based Nehalem-EX system with MKL?

Posted: August 6th, 2010, 9:58am MDT by Jeff Kataoka (Intel)

A new article has been published that discusses methods to get higher performance on NUMA-based Nehalem-EX system with MKL without controlling NUMA policy for shared memory. Check it out today!

To discover more Parallel Programming resources and tools, visit the Parallel Programming Community on the Intel Software Network. Are you developing software for commercial use? Learn about the Intel Software Partner Program today and discover how the program can help you deliver innovative solutions to meet your users' demands. Learn More
Writing Secure Self-Updating Code

Posted: August 6th, 2010, 2:03am MDT by Ylian Saint-hilaire (Intel)

Part of the Mesh Networking project I am working on depends on being able to perform fast, scalable mass updates of all of the nodes on the network. This is quite a task. Even if the mesh agent is small, if it's installed on many machines it can represent a lot of data.

To make the process scalable, I use the peer-to-peer network itself as a update system. Nodes can get updates from the central server, but they can also update each other. This is where there is real scalability gains. Nodes on a fast Intranet performing updates of other nodes on the same network. You cut the amount of WAN network usage and cut the about of traffic on the server (good for me!).

But this entire process depends on security. You have to be able to verify that an update is authentic, is truly a better version and is for the same machine architecture as your own. On my mesh agents, there is an HTTP link to the executable of the agent itself. No need for separate storage, just use the binary file you are running right now and the source of the update for other nodes.

On Windows, there is a known process for signing binaries. It's called Authenticode and I use it for the mesh agents. It's nice because it's presumably well reviewed, and you have good support for it in Windows. You can right click on an executable and see the signature in a new tab.

For Linux, I looked around and could not find a executable (ELF) signing format. Luckily, yesterday I tried appending junk at the end of my executable and it kept working fine, so I built my own signature block that I append at the end of the Linux binary. Since the mesh network makes heavy use of signed data blocks, I used the exact same code to sign the executable and append the result at the end.

Tonight, I finally got my Linux executable to start self-checking it's own signature each time it runs, just like my Windows version. It also checks the signed version and architecture type before doing an update. Lastly, I have my own signing tool and modified the agent's makefile to automatically sign the code. Note that when compiling a release executable, I also strip all the symbols before performing the signature.

That's it. Hopefully, I will have Linux support widely avaialble soon.
Ylian
http://meshcentral.homeip.net
New technical paper: Getting High Performance on NUMA-based Nehalem-EX System Without Controlling NUMA Policy for Shared Memory, New Brashears Blog Discusses the Upcoming (Monday Aug 9) Launch of Part 2 of the Intel® Threading Challenge 2010

Posted: August 5th, 2010, 5:54pm MDT by Kathy Farrel (Intel)

Learn how using a utility as numactl^l on that system under Linux, namely controlling NUMA policy for shared memory, improves performance dramatically by reading Getting High Performance on NUMA-based Nehalem-EX system with MKL Without Controlling NUMA Policy for Shared Memory by Intel's Michael Chuvelev.

Clay Brashears has written a new blog entitled "Let the Parallel Coding Resume!" and he talks about Part 2 of the Intel® Threading Challenge 2010 which kicks off this coming Monday, August 9, as well as the really great prizes to be won. Click here to send an email and obtain a contest account.

Good luck with your entries!

Kathy
Let the Parallel Coding Resume!

Posted: August 5th, 2010, 12:10pm MDT by Clay Breshears (Intel)

Phase 1 of the Intel Threading Challenge 2010contest ended a few weeks ago. If you participated in the Phase 1 contest, I hope you got some rest and could enjoy a portion of the Summer months; if you didn't participate, I hope you were studying up on your parallel methods, algorithms and programming libraries. For the judging and support staff it has been a busy past couple of weeks. For one thing, I discussed how I would have approached solving both of the Phase 1 Apprentice level problems on a recent episode (#88) of Parallel Programming Talk.

We've been getting ready for the Phase 2 launch on Monday, 09 AUG. Phase 2 is where you can earn the big prizes. If you didn't have the chance to enter solutions for any of the Phase 1 problems, don't worry. The problems in Phase 1 have been put behind us and we'll be starting everyone off with a blank slate. Your top three scoring entries for Phase 2 submissions will be used to determine the overall contest winners. So, even if you miss one of the four problems, you still have the chance to take home a top prize.

The biggest addition to the contest for Phase 2 is the availability of a shared platform on which contestants can develop and tune their applications. The Intel(R) Manycore Testing Lab (MTL) will be made available to Threading Challenge contestants. Use of the MTL will give participants the opportunity to write and test their code on systems exactly configured to what the judges will be using to score submitted entries. No more guessing about if your code will build or how it will run. (There is no requirement to use the MTL for any part of the contest. It is strictly an optional alternative being made available to those that wish to use it.)

Having a shared machine available has always been a dream of the contest organizers and we're excited to see how this will work out for the Phase 2 portion of this year's contest. For more details on the MTL and how to apply for an account on the machine, see the Threading Challenge 2010 contest home page or click here to send an email to request an account.

With universities and colleges starting back to school soon, we hope that faculty will take advantage of the Threading Challenge contest by urging their students to participate and sharpen their parallel programming skills or to just have fun.

There are plenty of resources available through the ISN Parallel Programming Community pages to find help and advice about threaded coding. The Intel Guide for Developing Multithreaded Applications can be a good place to learn a trick or two that might give your code that extra performance boost to beat all others.

Everybody, at one time or other, feels they've got to prove something to the rest of the world. This is your chance to show off your parallel programming skills and come away with fame, glory, and prizes. I'm inviting you to code against and learn from and join the ranks of the next generation of parallel programming superstars.

(Disclaimer: Amount of fame and glory achieved may vary. Fame and glory unavailable where prohibited by law.)

Detecting the install path for Microsoft Visual Studio from C++

Posted: August 5th, 2010, 8:56am MDT by Doug Binks (Intel)

During a recent project I needed to find out the install location of the Microsoft Visual Studio version a user has, in order to be able to run compiles from the command line, and run Vcvars32.bat to set up the required environment variables. Though there's enough information on the web do figure out how to do this, no one article had the complete solution so I thought I'd post mine here.

The following code sample is from the cpp file of a win32 project. I've tested it against installs of 2008 and 2010 versions, along with the express versions - but if you find a problem using the code post a response and I'll try to help or fix the code sample. Note the use of KEY_WOW64_32KEY to ensure 64bit versions use the 32bit key to get hold of the right path.


#include "stdafx.h"

//following headers required for GetPathsOfVisualStudioInstalls
#include "windows.h"
#include <string>
#include <vector>

//following header required for sample main io
#include <iostream>
#include <conio.h>

using namespace std;

struct VSVersionInfo
{
	int				Version;
	std::wstring	Path;
};

void GetPathsOfVisualStudioInstalls( std::vector<VSVersionInfo>* pVersions )
{
	std::wstring keyName = L"SOFTWARE\\Microsoft\\VisualStudio\\SxS\\VC7";

	std::wstring valueName[3];
	valueName[0] = L"8.0";
	valueName[1] = L"9.0";
	valueName[2] = L"10.0";
	TCHAR value[MAX_PATH];
	DWORD size = MAX_PATH;

	HKEY key;
	LONG retKeyVal = RegOpenKeyEx(
				  HKEY_LOCAL_MACHINE,	//__in        HKEY hKey,
				  keyName.c_str(),			//__in_opt    LPCTSTR lpSubKey,
				  0,					//__reserved  DWORD ulOptions,
				  KEY_READ | KEY_WOW64_32KEY,		//__in        REGSAM samDesired,
				  &key					//__out       PHKEY phkResult
				);

	for( int i = 2; i >= 0; --i )
	{
		LONG retVal = RegGetValue(
					  key,	//__in         HKEY hkey,
					  NULL,			//__in_opt     LPCTSTR lpSubKey,
					  valueName[i].c_str(),	//__in_opt     LPCTSTR lpValue,
					  RRF_RT_ANY,			//__in_opt     DWORD dwFlags,
					  NULL,					//__out_opt    LPDWORD pdwType,
					  (void*)value,			//__out_opt    PVOID pvData,
					  &size					//__inout_opt  LPDWORD pcbData
					);
		if( ERROR_SUCCESS == retVal )
		{
			VSVersionInfo vInfo;
			vInfo.Version = i + 8;
			vInfo.Path = value;
			vInfo.Path += L"bin\\";
			pVersions->push_back( vInfo );
		}
	}

	RegCloseKey( key );

	return;
}

int _tmain(int argc, _TCHAR* argv[])
{
	std::vector<VSVersionInfo> Versions;
	GetPathsOfVisualStudioInstalls( &Versions );

	for( size_t i = 0; i < Versions.size(); ++i)
	{
		wcout << "Version: " << Versions[i].Version << " located at:" << endl;
		wcout << Versions[i].Path << endl;
	}

	wcout << "Press a key to exit." << endl;

	_getch();

	return 0;
}

Part 2 of Jim Dempsey's Technical Paper Posted, Misc. Announcements

Posted: August 4th, 2010, 7:21pm MDT by Kathy Farrel (Intel)

Enclosure: [download]

I want to take a few minutes to tell you about some happenings on the Parallel Programming Community. New high-quality reading is arriving almost daily. For example, Part 2 of ISN Black Belt Jim Dempsey's 5-part article "Superscalar Programming 101 (Matrix) " was just released today. Part 1 has been viewed a gazillion times already - be sure to check these out as they are published (in one-week increments starting Wednesday, July 28). Jim is currently doing some lab work that will be reported on in later article installments.

------------

I need to mention again the CT Tutorial being given at the 19th International Parallel Architectures and Compilation Techniques (PACT) Sept. 11-15 in Vienna Austria. Intel Engineer Dr. Michael Klemm with present the tutorial. Register now!

Intel® CT technology provides a generalized data parallel programming solution that frees application developers from dependencies on particular low-level parallelism mechanisms or hardware architectures. Here is more info about CT.

------------

Get ready for the Threading Challenge Part 2 - to be launched next Monday, August 9. Book mark the URL for the Parallel Programming Community Home Page as you will find a link, to info on the ongoing Challenge, next week and beyond.

------------

And last but not least - the Intel Developer's Forum is right around the corner - September 13-15 at the Moscone Center in San Francisco.

You're going aren't you? I'll see you there!

Kathy
MeshCentral now hooked up to Twitter

Posted: August 3rd, 2010, 10:46pm MDT by Ylian Saint-hilaire (Intel)

For the last few weeks, my co-worker and I have been working on this crazy idea of hooking up your home or small office computers to Twitter. The idea is simple: If all goes as planned the web site I am building will eventually allow your computer to complain on Twitter if something goes wrong. Yes, there is a possibility your family and friends will see that your computer has not booted properly this morning. Why would you want that? Well, as I said before it's crazy. No need to elaborate.

So, I am working on this experimental web site called MeshCentral. It allows someone to hook up computers to the site using a special peer-to-peer agent. You install the agent on any machine and a few seconds later, that computer is on the web site and you can monitor and interact with it. Now, today for the first time, we got our web site hooked up with Twitter and so, we could start streaming what is going on. Fear not, this feature will be only activated if the user wants it activated and by default it's off. Still, today we took the first step and started our MeshCentral Twitter channel. The server sends updates about it's state in a very generic way, indicating if it's found or lost contact with computers and what else is going on. The information is vague because the specific computer names, etc. are private. But hopefully in a few weeks, we will have a new settings page and you can opt to have your own computer's information sent to a public or private Twitter account.

So, the new Twitter channel is at: [twitter.com]

As we evolve the service, it's hoped that we will improve the quality of the information that can be displayed and turn this into something that is truly interesting.

Ylian
meshcentral.homeip.net
What does your laptop or netbook skin look like?

Posted: August 3rd, 2010, 8:37pm MDT by Gina Bovara (Intel)

Hi everyone, just a fun post to brighten up your week!

My laptop "art" was featured as the Shwaag Sighting of the week this week - click the link to view it! Of course, I've got the big Intel logo on there ... would you expect anything less? :-)

It got me wondering ... how many of you are into skinning your laptop or netbook with skins and stickers? Does anyone have anything really cool that they'd like to share showing off an Intel sticker or logo? Post a link to your image here and the best ones will make it to our Facebook page and you'll be (almost) famous!
Parallelism Exposure - It's Not That Hard!

Posted: August 3rd, 2010, 6:19pm MDT by Dan Ernst
Over the last few years, I've been talking to a lot of people about the conversion of our hardware to a parallel base and what that might mean for undergraduate CS education. Although it doesn't surprise me much any more, I was initially pretty startled by how negative a lot of people were to the idea of making any curriculum changes. When it comes down to it, though, I don't particularly blame them. After all:
1. CS Curricula are already jam-packed full of "must-teach" materials, so it is daunting to think about adding to the load.
2. While CS faculty are constantly picking up new technologies and language features, being asked to learn an entirely different paradigm seems impractical in the context of other pressures, and...
3. That paradigm (parallel computing) has a longstanding stigma within the CS community as being an overly complex, extremely low-level, and largely archaic field only practiced by specialists.
Once I got a feel for these pressures (especially being a new faculty member myself, at the time), I wanted to try to convince people that the perceived difficulty of injecting a little parallelism into their classes really wasn't the mammoth task that they think it is. So, I went to a colleague of mine and asked him what kind of labs he was doing. What we found was that many of the tasks he was assigning to students were ripe for easy parallelism using the language we were already using (Java) on platforms we already had (multicore lab computers), within the context of the course material we were already teaching.

We published our results in ITiCSE a couple of years ago, which includes several example assignments and labs. We've gotten a bit of feedback from educators since then, and it's been very positive. Hopefully, we've persuaded a few people that this isn't as massive (or archaic) it initially appears.

I'm always on the lookout for more "simple ideas". I'd love to hear yours!

(Cross-posted at my personal blog)
Adobe and Intel Application Lab was a success!

Posted: July 30th, 2010, 10:39pm MDT by Gina M Bovara

We had a blast at the Adobe and Intel Application Lab in San Francisco on July 21! There were approximately 140 attendees who came down for pizza, beer and lots of technical discussion – and another 40 users watched via our live webcast. The event was just the beginning of new programs to drive AIR application momentum for Intel AppUp Center, and began with an announcement of the availability of the Adobe AIR SDK.
read more
New ISN Parallel Programming Manager - Lots to Learn, Many Community Members to Meet

Posted: July 30th, 2010, 6:18pm MDT by Kathy Farrel (Intel)
I am really happy about being the new ISN Parallel Programming Community Manager. (I had previously been in charge of the Manageability Community.) I've been spinning up, thanks to former community manager Aaron Tersteeg. I've been busy for the last month learning as much as I can about this different focus area: Multi-Core, and especially about Parallel Programming. These are proving to be fascinating subjects and I appreciate the help I'm receiving from community members.

A few years ago I worked as a technical writer on an initial multi-core reference design project. At the time I wondered how many cores there would eventually be. I understand that the number is 12 now. Wow - how many cores are too many? Is the sky the limit? We'll have to wait and see. But being close to this technology and the people who create it is just as exciting now for me as it was back then.

In the meantime I'll concentrate on this community - ensuring that it keeps growing and that members are getting just what they need as well as have opportunities to contribute to the whole. I'm sure I'll be making some changes and appreciate any and all feedback on the community. What's good and what could be better? Can I help you get on the path to become an ISN Black Belt? If you are on a Principal Engineer or Senior Engineer career path, ISN's Black Belt Program is a superb vehicle to help you get there. Drop me a line and we can create a plan to utilize this unique program to your advantage.

As always on this community we've gotten a lot of new content in the past few weeks including new Blogs, articles and Parallel Programming Talk shows. Here are some titles.
Look for some very interesting happenings on the Parallel Programming Talk show in the next few weeks. You will definitely want to view these. :-) And then we have episodes of ISN-TV coming up in September at the Intel Developer Forum to look forward to.

Hey - it's 5pm on Friday - let the weekend begin - enjoy it wherever you happen to be!

Regards

Kathy

PS:Are you developing software for commercial use? Learn about the Intel Software Partner Program today and discover how the program can help you deliver innovative solutions to meet your users' demands.
How to Be More App Than Application: Tips for AppUp Development

Posted: July 29th, 2010, 4:08pm MDT by Bob Duffy (Intel)

I have about 70 applications on my netbook AppUp client and these apps run the spectrum. As I use these apps I'm often struck when one stands out as being a good app experience. I believe that experience is also what I tend to see in mobile apps for iPhone, iPad and Android. The difference is often not the overall quality of the app, but it's something that defines it more as an app and less than an application. For netbooks this is a distinction I see more and more developers grasping as they publish in AppUp.

read more
Building your Parallel Programming Skills - Check out Superscalar Programming 101 (Matrix Multiply) Part 1

Posted: July 29th, 2010, 12:49pm MDT by Jeff Kataoka (Intel)

Looking at ways to build up your parallel programming skills? Or just interested in reviewing different methods? I think you would find it valuable to read this new article, "Superscalar Programming 101 (Matrix Multiply) Part 1", written by Jim Dempsey, an Intel Black Belt Software Developer. This multi-part article teaches you a methodology of how to interpret the statistics gathered during test runs and then use those interpretations at improving your parallel code.

To discover more Parallel Programming resources and tools, visit the Parallel Programming Community on the Intel Software Network. Are you developing software for commercial use? Learn about the Intel Software Partner Program today and discover how the program can help you deliver innovative solutions to meet your users' demands. Learn More
Manage your computers using an Apple iPad.

Posted: July 28th, 2010, 1:58pm MDT by Ylian Saint-hilaire (Intel)

I have been working on a VT100 terminal in Javascript that works along with MeshCentral to allow someone to manage your computers from anywhere. Well, last night I got the terminal pretty much done and worked on a variant for the Apple iPad. It's the same page, but I used Javascript to detect the iPad and make a few changes to the way input is collected.

In any case, the result is the screen below. You can log into MeshCentral, select a computer and then select the terminal screen to connect and manage the computer remotely. The connection will be established to the mesh agent who has a built-in command shell. You can also drop to the Windows command prompt or the Linux shell depending on the operating system. In the screen below, I happen to be managing a Linux machine and so, I ran "top" to get list system status.

By the way, the first version of my terminal used the HTML5 canvas construct, but this is not what I am using now. Since "canvas" was not supported in Internet Explorer, I used an HTML alternative based around the <pre> tag. This seems to work pretty well across all browsers.

I will be updating MeshCentral with the latest version of the terminal in the next few hours and work on more security and permission granting so to guard this feature.

Ylian
meshcentral.homeip.net
OSCON 2010 Wrap Up and Highlights

Posted: July 28th, 2010, 1:54pm MDT by Lisa Hoover

The O'Reilly Open Source Convention (OSCON) 2010 wrapped up a few days ago and, by all reports, it was another smashing success. Awards were handed out to individuals who've made significant contributions to the open source community, speakers came from all over the world to share their knowledge, and breakout sessions brought individuals together to collaborate on everything from PHP frameworks to managing open source projects.

There were plenty of notable announcements, presentations, and ideas flowing during OSCON:

Hosting provider Rackspace surprised a lot of folks with the release of its Apache 2-licensed cloud platform called OpenStack. Since the project incorporates some of the same technology used by the NASA Nebula Cloud Platform, Rackspace generated a huge amount of buzz across the Internet when the news broke.

Facebook's Senior Open Programs Manager, David Recordon, used his keynote session to give conference-goers a peek under the hood of the infrastructure used at the social networking behemoth. Check out Recordon's presentation slides or watch the video for a better understanding of how the LAMP stack's emerging focus on database innovations are driving data management at Facebook.

Intel's Dirk Hohndel, Chief Linux and Open Source Technologist of the Software and Solutions Group gave a terrific keynote about the MeeGo project. Attendees got an inside look at how the development MeeGo 1.1 is coming along and Intel's future plans for the open source mobile operating system. For those who wanted a more technical look at MeeGo, Intel's Senior Principal Engineer Sunil Saxena gave an in-depth presentation that took a look at the whole MeeGo stack from its core operating system and hardware layer to apps and APIs. Check out MeeGo's OSCON wiki page for links to all things MeeGo at the convention.

In light of Web and cloud services, Splunk Community Manager John Mark Walker asked if FOSS is even necessary anymore. In a service world, says Walker, "interface is everything." Even if it's built on free software, users are still at the mercy of the interface -- which is "only as good as its creator." As a result, rules and policies make sense even for free software when it comes to creating solid, reliable Web services. The good news, says Walker, is that effective rules and the sustainable systems that occur as a result "happen because a lot of good people work really hard to make them happen." The FOSS community loves its open data, formats, and initiatives, and with the right guidance, really strong ecosystem can emerge for creating powerful Web services across the Internet.

Aaron Williamson from the Software Freedom Law Center gave an excellent presentation on why Your Smartphone May Not be as Open as You Think. He says that just because a mobile device ships with an open source operating system, patent restrictions and FCC regulations still prevent vendors from creating a truly open phone. To learn more about what Williamson had to say about the issue and what ideas he has for overcoming the challenges open source smartphone vendors face, check out PreCentral.net's man-on-the-ground blog post by OSCON attendee Robert Werlinger.

Highlights and slide decks from many of the presentations are available at the OSCON 2010 Web site, along with dozens of videos and full recaps of all the keynotes. If you missed this year's convention, plan ahead to catch the next one in 2011. There are plenty of open source conferences to attend around the country, but the sheer amount of information and education available at OSCON makes it a don't-miss event.